aboutsummaryrefslogtreecommitdiff
path: root/target
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2020-11-10 14:59:20 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-11-10 14:59:20 +0000
commit3e7d06d05a3689972171ad6a289315d54ea2e915 (patch)
tree844ca7d9ffbec29d846c016cb97d23087c80bde8 /target
parent879860ca706fa1ef47ba511c49a6e2b1b49be9b7 (diff)
parentb6c56c8a9a4064ea783f352f43c5df6231a110fa (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201110' into staging
target-arm queue: * hw/arm/Kconfig: ARM_V7M depends on PTIMER * Minor coding style fixes * docs: add some notes on the sbsa-ref machine * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals * target/arm: Fix neon VTBL/VTBX for len > 1 * hw/arm/armsse: Correct expansion MPC interrupt lines * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary * hw/arm/nseries: Check return value from load_image_targphys() * tests/qtest/npcm7xx_rng-test: count runs properly * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check # gpg: Signature made Tue 10 Nov 2020 11:17:45 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201110: target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check tests/qtest/npcm7xx_rng-test: count runs properly hw/arm/nseries: Check return value from load_image_targphys() hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ hw/arm/armsse: Correct expansion MPC interrupt lines target/arm: Fix neon VTBL/VTBX for len > 1 hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals docs: add some notes on the sbsa-ref machine target/arm: add space before the open parenthesis '(' target/arm: Don't use '#' flag of printf format target/arm: add spaces around operator ssi: Fix bad printf format specifiers hw/arm/Kconfig: ARM_V7M depends on PTIMER Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/arch_dump.c8
-rw-r--r--target/arm/arm-semi.c8
-rw-r--r--target/arm/helper.c2
-rw-r--r--target/arm/helper.h2
-rw-r--r--target/arm/op_helper.c23
-rw-r--r--target/arm/translate-a64.c4
-rw-r--r--target/arm/translate-neon.c.inc50
-rw-r--r--target/arm/translate.c2
8 files changed, 44 insertions, 55 deletions
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 7693e17e96..0184845310 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -114,8 +114,8 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
for (i = 0; i < 32; ++i) {
uint64_t *q = aa64_vfp_qreg(env, i);
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
}
if (s->dump_info.d_endian == ELFDATA2MSB) {
@@ -125,8 +125,8 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
*/
for (i = 0; i < 32; ++i) {
uint64_t tmp = note.vfp.vregs[2*i];
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
- note.vfp.vregs[2*i+1] = tmp;
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
+ note.vfp.vregs[2 * i + 1] = tmp;
}
}
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index 8718fd0194..c1df664f7e 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -755,7 +755,7 @@ target_ulong do_arm_semihosting(CPUARMState *env)
if (use_gdb_syscalls()) {
arm_semi_open_guestfd = guestfd;
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
- (int)arg2+1, gdb_open_modeflags[arg1]);
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
} else {
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
if (ret == (uint32_t)-1) {
@@ -852,7 +852,7 @@ target_ulong do_arm_semihosting(CPUARMState *env)
GET_ARG(1);
if (use_gdb_syscalls()) {
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
- arg0, (int)arg1+1);
+ arg0, (int)arg1 + 1);
} else {
s = lock_user_string(arg0);
if (!s) {
@@ -870,7 +870,7 @@ target_ulong do_arm_semihosting(CPUARMState *env)
GET_ARG(3);
if (use_gdb_syscalls()) {
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
- arg0, (int)arg1+1, arg2, (int)arg3+1);
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
} else {
char *s2;
s = lock_user_string(arg0);
@@ -896,7 +896,7 @@ target_ulong do_arm_semihosting(CPUARMState *env)
GET_ARG(1);
if (use_gdb_syscalls()) {
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
- arg0, (int)arg1+1);
+ arg0, (int)arg1 + 1);
} else {
s = lock_user_string(arg0);
if (!s) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6854591986..11b0803df7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12508,7 +12508,7 @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
uint32_t sum;
sum = do_usad(a, b);
sum += do_usad(a >> 8, b >> 8);
- sum += do_usad(a >> 16, b >>16);
+ sum += do_usad(a >> 16, b >> 16);
sum += do_usad(a >> 24, b >> 24);
return sum;
}
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 774d2cddb5..ff8148ddc6 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -245,7 +245,7 @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index b1065216b2..aa13b978c0 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -68,21 +68,24 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
cpu_loop_exit_restore(cs, ra);
}
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
- uint32_t maxindex)
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
+ uint64_t ireg, uint64_t def)
{
- uint32_t val, shift;
- uint64_t *table = vn;
+ uint64_t tmp, val = 0;
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
+ uint32_t base_reg = desc >> 2;
+ uint32_t shift, index, reg;
- val = 0;
- for (shift = 0; shift < 32; shift += 8) {
- uint32_t index = (ireg >> shift) & 0xff;
+ for (shift = 0; shift < 64; shift += 8) {
+ index = (ireg >> shift) & 0xff;
if (index < maxindex) {
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
- val |= tmp << shift;
+ reg = base_reg + (index >> 3);
+ tmp = *aa32_vfp_dreg(env, reg);
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
} else {
- val |= def & (0xff << shift);
+ tmp = def & (0xffull << shift);
}
+ val |= tmp;
}
return val;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 072754fa24..1867ec293f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -12114,7 +12114,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
__func__, insn, fpopcode, s->pc_curr);
g_assert_not_reached();
}
@@ -13121,7 +13121,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7f: /* FSQRT (vector) */
break;
default:
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
g_assert_not_reached();
}
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 59368cb243..2403825d15 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -2861,9 +2861,8 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
{
- int n;
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
- TCGv_ptr ptr1;
+ TCGv_i64 val, def;
+ TCGv_i32 desc;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -2875,47 +2874,34 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
return false;
}
- if (!vfp_access_check(s)) {
- return true;
- }
-
- n = a->len + 1;
- if ((a->vn + n) > 32) {
+ if ((a->vn + a->len + 1) > 32) {
/*
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
* helper function running off the end of the register file.
*/
return false;
}
- n <<= 3;
- tmp = tcg_temp_new_i32();
- if (a->op) {
- read_neon_element32(tmp, a->vd, 0, MO_32);
- } else {
- tcg_gen_movi_i32(tmp, 0);
+
+ if (!vfp_access_check(s)) {
+ return true;
}
- tmp2 = tcg_temp_new_i32();
- read_neon_element32(tmp2, a->vm, 0, MO_32);
- ptr1 = vfp_reg_ptr(true, a->vn);
- tmp4 = tcg_const_i32(n);
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
+ desc = tcg_const_i32((a->vn << 2) | a->len);
+ def = tcg_temp_new_i64();
if (a->op) {
- read_neon_element32(tmp, a->vd, 1, MO_32);
+ read_neon_element64(def, a->vd, 0, MO_64);
} else {
- tcg_gen_movi_i32(tmp, 0);
+ tcg_gen_movi_i64(def, 0);
}
- tmp3 = tcg_temp_new_i32();
- read_neon_element32(tmp3, a->vm, 1, MO_32);
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp4);
- tcg_temp_free_ptr(ptr1);
+ val = tcg_temp_new_i64();
+ read_neon_element64(val, a->vm, 0, MO_64);
- write_neon_element32(tmp2, a->vd, 0, MO_32);
- write_neon_element32(tmp3, a->vd, 1, MO_32);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp3);
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
+ write_neon_element64(val, a->vd, 0, MO_64);
+
+ tcg_temp_free_i64(def);
+ tcg_temp_free_i64(val);
+ tcg_temp_free_i32(desc);
return true;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 29ea1eb781..f7d4ee393b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9171,7 +9171,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
- Hardware watchpoints.
Hardware breakpoints have already been handled and skip this code.
*/
- switch(dc->base.is_jmp) {
+ switch (dc->base.is_jmp) {
case DISAS_NEXT:
case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, dc->base.pc_next);