diff options
| author | Emanuele Giuseppe Esposito <eesposit@redhat.com> | 2023-02-01 08:57:59 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-05-18 08:53:50 +0200 |
| commit | 22e1094ca82d5518c1b69aff3e87c550776ae1eb (patch) | |
| tree | 1e837e7055bc8acc78d78782cdfd516f7f79ee19 /target | |
| parent | 0e7e3bf1a552c178924867fa7c2f30ccc8a179e0 (diff) | |
target/i386: add support for FB_CLEAR feature
As reported by the Intel's doc:
"FB_CLEAR: The processor will overwrite fill buffer values as part of
MD_CLEAR operations with the VERW instruction.
On these processors, L1D_FLUSH does not overwrite fill buffer values."
If this cpu feature is present in host, allow QEMU to choose whether to
show it to the guest too.
One disadvantage of not exposing it is that the guest will report
a non existing vulnerability in
/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
because the mitigation is present only when the cpu has
(FLUSH_L1D and MD_CLEAR) or FB_CLEAR
features enabled.
Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
Message-Id: <20230201135759.555607-3-eesposit@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e5c813199a..a61cd6d99d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1050,7 +1050,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", "taa-no", NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "fb-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3c6f9226e1..7201a71de8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1018,6 +1018,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) #define MSR_ARCH_CAP_TAA_NO (1U << 8) +#define MSR_ARCH_CAP_FB_CLEAR (1U << 17) #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) |