diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-25 17:05:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-25 17:05:22 +0100 |
| commit | e3955ae93f5151ad2e982440b7c8d3776a9afee2 (patch) | |
| tree | 355a6ea83d17c09ba98cedbab0330e316d43e53d /target | |
| parent | 3593b8e0a2146a885f93d71c754757bb2c03864e (diff) | |
| parent | 3ef6434409c575e11faf537ce50ca05426c78940 (diff) | |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging
Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext
- Fix GDB CSR XML generation
- QOMify the SiFive UART
- Add support for the OpenTitan timer
# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210624-2:
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
hw/timer: Initial commit of Ibex Timer
hw/char/ibex_uart: Make the register layout private
hw/char: QOMify sifive_uart
hw/char: Consistent function names for sifive_uart
target/riscv: gdbstub: Fix dynamic CSR XML generation
target/riscv: Use target_ulong for the DisasContext misa
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/gdbstub.c | 2 | ||||
| -rw-r--r-- | target/riscv/translate.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ca78682cf4..a7a9c0b1fe 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -170,7 +170,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) for (i = 0; i < CSR_TABLE_SIZE; i++) { predicate = csr_ops[i].predicate; - if (predicate && !predicate(env, i)) { + if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { if (csr_ops[i].name) { g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c6e8739614..62a7d7e4c7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -47,7 +47,7 @@ typedef struct DisasContext { bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; - uint32_t misa; + target_ulong misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for |