diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 09:02:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:17 +0100 |
| commit | 2ec0dcf034b6954eb6d0b03ae83fba015e263c27 (patch) | |
| tree | e10b2c0f39df07d6cd589dc87a493b576b415006 /target | |
| parent | 2a4b939cf865fe5edd0f3dccf1b4ba6c3ca8b904 (diff) | |
target/arm: Implement MVE VCVT between fp and integer
Implement the MVE "VCVT (between floating-point and integer)" insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/mve.decode | 7 | ||||
| -rw-r--r-- | target/arm/translate-mve.c | 32 |
2 files changed, 39 insertions, 0 deletions
diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d93083065d..89b8c6fc8e 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -798,3 +798,10 @@ VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1 ... 0 @vcvt VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt + +# VCVT between floating point and integer (halfprec and single); +# VCVT_<from><to>, S = signed int, U = unsigned int, F = float +VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op +VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op +VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op +VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 9269dbc332..351033af1e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -543,6 +543,38 @@ DO_1OP(VQNEG, vqneg) DO_1OP(VMAXA, vmaxa) DO_1OP(VMINA, vmina) +/* + * For simple float/int conversions we use the fixed-point + * conversion helpers with a zero shift count + */ +#define DO_VCVT(INSN, HFN, SFN) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##HFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_##SFN(env, qd, qm, tcg_constant_i32(0)); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] = { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VCVT(VCVT_SF, vcvt_sh, vcvt_sf) +DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf) +DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) +DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ |