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authorGiuseppe Musacchio <thatlemon@gmail.com>2020-11-09 10:17:11 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2020-12-14 15:54:09 +1100
commitbcb0b7b1a1c05707304f80ca6f523d557816f85c (patch)
tree8f1831607a6058a97e0cbb01205701d329c7fc81 /target
parent91699dbf30a94dea2575ae193412c364c7f3a5fd (diff)
ppc/translate: Rewrite gen_lxvdsx to use gvec primitives
Make the implementation match the lxvwsx one. The code is now shorter smaller and potentially faster as the translation will use the host SIMD capabilities if available. No functional change. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Message-Id: <a463dea379da4cb3a22de49c678932f74fb15dd7.1604912739.git.thatlemon@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
-rw-r--r--target/ppc/translate/vsx-impl.c.inc46
1 files changed, 23 insertions, 23 deletions
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 075f063e98..b817d31260 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -75,29 +75,6 @@ static void gen_lxvd2x(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
-static void gen_lxvdsx(DisasContext *ctx)
-{
- TCGv EA;
- TCGv_i64 t0;
- TCGv_i64 t1;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrh(xT(ctx->opcode), t0);
- tcg_gen_mov_i64(t1, t0);
- set_cpu_vsrl(xT(ctx->opcode), t1);
- tcg_temp_free(EA);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
-}
-
static void gen_lxvw4x(DisasContext *ctx)
{
TCGv EA;
@@ -169,6 +146,29 @@ static void gen_lxvwsx(DisasContext *ctx)
tcg_temp_free_i32(data);
}
+static void gen_lxvdsx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i64 data;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+
+ gen_addr_reg_index(ctx, EA);
+
+ data = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
+ tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
+
+ tcg_temp_free(EA);
+ tcg_temp_free_i64(data);
+}
+
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{