diff options
| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-09 09:08:56 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-02-09 09:08:56 +0100 |
| commit | 7df40c5414b2f5e213fa30005f1600a429660cc5 (patch) | |
| tree | 533058fa5068b3130091501ed29eb202b0b27e56 /target | |
| parent | 3c3fa438f6c008e536c809c20530b423ff877b2f (diff) | |
target/ppc: 7xx: Software TLB cleanup
This code applies only to the 7xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/excp_helper.c | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2bbfc25d2b..dd373a4d5b 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -745,7 +745,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - int excp_model = env->excp_model; target_ulong msr, new_msr, vector; int srr0, srr1; @@ -904,26 +903,13 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ - switch (excp_model) { - case POWERPC_EXCP_6xx: - /* Swap temporary saved registers with GPRs */ - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { - new_msr |= (target_ulong)1 << MSR_TGPR; - hreg_swap_gpr_tgpr(env); - } - /* fall through */ - case POWERPC_EXCP_7xx: - ppc_excp_debug_sw_tlb(env, excp); + ppc_excp_debug_sw_tlb(env, excp); + + msr |= env->crf[0] << 28; + msr |= env->error_code; /* key, D/I, S/L bits */ + /* Set way using a LRU mechanism */ + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - msr |= env->crf[0] << 28; - msr |= env->error_code; /* key, D/I, S/L bits */ - /* Set way using a LRU mechanism */ - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; - default: - cpu_abort(cs, "Invalid TLB miss exception\n"); - break; - } break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ case POWERPC_EXCP_SMI: /* System management interrupt */ |