diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2017-07-18 01:55:38 -0300 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
| commit | 08d64e0db02e826b063d2b0d8b84f1cb1f7306c9 (patch) | |
| tree | 6355fc749b45f1a212a2499ee5a031b7628f78d8 /target | |
| parent | 0b1183e315cce99102898bda54f69b685157a507 (diff) | |
target/sparc: optimize gen_op_mulscc() using deposit op
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sparc/translate.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 67a83b77cc..d13173275f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -632,11 +632,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) // b2 = T0 & 1; // env->y = (b2 << 31) | (env->y >> 1); - tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); - tcg_gen_shli_tl(r_temp, r_temp, 31); tcg_gen_extract_tl(t0, cpu_y, 1, 31); - tcg_gen_or_tl(t0, t0, r_temp); - tcg_gen_andi_tl(cpu_y, t0, 0xffffffff); + tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); // b1 = N ^ V; gen_mov_reg_N(t0, cpu_psr); |