diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2019-10-30 14:03:38 +0100 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2020-04-30 12:11:03 +0200 |
| commit | 622cc7305cdfe2402950d21bc2160a76646bf259 (patch) | |
| tree | f4273d6cc62eb3fb97f9ff7e58da6b1ee2357e13 /target | |
| parent | 5143fdf36f78bd4c11c4bacedfdbd44365aa5781 (diff) | |
target/microblaze: Add the div-zero-exception property
Add the div-zero-exception property to control if the core
traps divizions by zero.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/microblaze/cpu.c | 4 | ||||
| -rw-r--r-- | target/microblaze/cpu.h | 1 | ||||
| -rw-r--r-- | target/microblaze/op_helper.c | 5 |
3 files changed, 8 insertions, 2 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2cc6b1513c..4211f50c11 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) PVR2_DOPB_BUS_EXC_MASK : 0) | (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.div_zero_exception ? + PVR2_DIV_ZERO_EXC_MASK : 0) | (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | (cpu->cfg.opcode_0_illegal ? @@ -280,6 +282,8 @@ static Property mb_properties[] = { cfg.iopb_bus_exception, false), DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, cfg.illegal_opcode_exception, false), + DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, + cfg.div_zero_exception, false), DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, cfg.opcode_0_illegal, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 71d7317a58..3c07f9b3f7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -305,6 +305,7 @@ struct MicroBlazeCPU { bool iopb_bus_exception; bool illegal_opcode_exception; bool opcode_0_illegal; + bool div_zero_exception; char *version; uint8_t pvr; } cfg; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 18677ddfca..f3b17a95b3 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { + MicroBlazeCPU *cpu = env_archcpu(env); + if (b == 0) { env->sregs[SR_MSR] |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) - && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { + if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } |