diff options
| author | Yifei Jiang <jiangyifei@huawei.com> | 2020-08-14 11:58:19 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | c51a3f5d155b66b190192fcba49c52eb30c9eaab (patch) | |
| tree | 1cb3246d46065e00d1c78ae58a1be1a28609cec9 /target | |
| parent | 9435a8b3dd35f1f926f1b9127e8a906217a5518a (diff) | |
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.
In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 11 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 | ||||
| -rw-r--r-- | target/riscv/cpu_helper.c | 4 |
3 files changed, 14 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..bcdce85c5e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = { "reserved" }; +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) +{ + if (async) { + return (cause < ARRAY_SIZE(riscv_intr_names)) ? + riscv_intr_names[cause] : "(unknown)"; + } else { + return (cause < ARRAY_SIZE(riscv_excp_names)) ? + riscv_excp_names[cause] : "(unknown)"; + } +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 383808bf88..d3589ae6ea 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dc7ae3e7b1..005880627e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -892,8 +892,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? - (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { |