diff options
| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-01-31 21:20:11 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | 95bd8daaafdff905ee4fa0620c097ad4eb2e8a13 (patch) | |
| tree | 97269019e4e6cb76250c828edadbc70c7f75076e /target | |
| parent | 7ad2878cfd8356e1b9c1097edae367507c182066 (diff) | |
RISC-V: Add initial support for T-Head C906
This patch adds the T-Head C906 to the list of known CPUs.
Selecting this CPUs will automatically enable the available
ISA extensions of the CPUs (incl. vendor extensions).
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 31 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 | ||||
| -rw-r--r-- | target/riscv/cpu_vendorid.h | 6 |
3 files changed, 38 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu = false; } +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.mmu = true; + cpu->cfg.ext_xtheadba = true; + cpu->cfg.ext_xtheadbb = true; + cpu->cfg.ext_xtheadbs = true; + cpu->cfg.ext_xtheadcmo = true; + cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_xtheadfmemidx = true; + cpu->cfg.ext_xtheadmac = true; + cpu->cfg.ext_xtheadmemidx = true; + cpu->cfg.ext_xtheadmempair = true; + cpu->cfg.ext_xtheadsync = true; + + cpu->cfg.mvendorid = THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ |