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authorFrank Chang <frank.chang@sifive.com>2021-12-10 15:43:25 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-12-20 14:51:36 +1000
commit13fb8c7b4252872c1b07fac5f0ea9231480c8463 (patch)
tree5d62fe66048e2098c27a5299a09bb91a58dba30c /target
parent6bc6fc96d1c9628c4c3514d277e541429e5b0b80 (diff)
target/riscv: zfh: add Zfh cpu property
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..0f808a5bee 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -629,6 +629,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),