diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2020-01-24 12:34:04 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2020-01-24 12:34:04 +0000 |
commit | ba2ed84fe6a78f64b2da441750fc6e925d94106a (patch) | |
tree | f2e5bc83442dcb7984e5240393953dea262eeb98 /target | |
parent | a43efa34c7d7b628cbf1ec0fe60043e5c91043ea (diff) | |
parent | 82f014671cf057de51c4a577c9e2ad637dcec6f9 (diff) |
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' into staging
RISC-V Patches for the 5.0 Soft Freeze, Part 1
This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):
* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.
Notably absent is the H extension implementation. That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes. This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".
# gpg: Signature made Tue 21 Jan 2020 22:55:28 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889
* remotes/palmer/tags/riscv-for-master-5.0-sf1:
target/riscv: update mstatus.SD when FS is set dirty
target/riscv: fsd/fsw doesn't dirty FP state
target/riscv: Fix tb->flags FS status
riscv: Set xPIE to 1 after xRET
riscv/sifive_u: fix a memory leak in soc_realize()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/cpu.h | 5 | ||||
-rw-r--r-- | target/riscv/csr.c | 3 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvd.inc.c | 1 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvf.inc.c | 1 | ||||
-rw-r--r-- | target/riscv/op_helper.c | 4 | ||||
-rw-r--r-- | target/riscv/translate.c | 2 |
6 files changed, 5 insertions, 11 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c..de0a8d893a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,10 +293,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags = TB_FLAGS_MSTATUS_FS; #else - *flags = cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - *flags |= TB_FLAGS_MSTATUS_FS; - } + *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..0e34c292c5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -341,8 +341,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - dirty = (riscv_cpu_fp_enabled(env) && - ((mstatus & MSTATUS_FS) == MSTATUS_FS)) | + dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); env->mstatus = mstatus; diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index 393fa0248c..ea1044f13b 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -43,7 +43,6 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); - mark_fs_dirty(ctx); tcg_temp_free(t0); return true; } diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 172dbfa919..e23cd639a6 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -52,7 +52,6 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); tcg_temp_free(t0); - mark_fs_dirty(ctx); return true; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 331cc36232..e87c9115bc 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_SIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_SPIE)); - mstatus = set_field(mstatus, MSTATUS_SPIE, 0); + mstatus = set_field(mstatus, MSTATUS_SPIE, 1); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus; @@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_MPIE)); - mstatus = set_field(mstatus, MSTATUS_MPIE, 0); + mstatus = set_field(mstatus, MSTATUS_MPIE, 1); mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 56b1b1fe7b..14dc71156b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -394,7 +394,7 @@ static void mark_fs_dirty(DisasContext *ctx) tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_temp_free(tmp); } |