diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2017-03-04 15:56:49 -0300 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-03-20 11:06:32 +0000 |
| commit | 989f2aa9af7f05c323761b66c0e299059a19b7b1 (patch) | |
| tree | 879822e344f4c5def344e1a4b8013fe162beecd1 /target | |
| parent | def74c0cf05722b2e502d4b4f1219966c5b0cbd3 (diff) | |
target-mips: remove old & unuseful comments
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 8b4a072ecb..1fe0ff39f2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5137,7 +5137,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ rn = "ContextConfig"; goto cp0_unimplemented; -// break; case 2: CP0_CHECK(ctx->ulri); tcg_gen_ld32s_tl(arg, cpu_env, @@ -5791,7 +5790,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; goto cp0_unimplemented; -// break; case 2: CP0_CHECK(ctx->ulri); tcg_gen_st_tl(arg, cpu_env, @@ -6454,7 +6452,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */ rn = "ContextConfig"; goto cp0_unimplemented; -// break; case 2: CP0_CHECK(ctx->ulri); tcg_gen_ld_tl(arg, cpu_env, @@ -7092,7 +7089,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; goto cp0_unimplemented; -// break; case 2: CP0_CHECK(ctx->ulri); tcg_gen_st_tl(arg, cpu_env, |