diff options
| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-01-28 13:15:05 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:05 +0100 |
| commit | 35f579f5c21682311039f84e2e81254937e6ff78 (patch) | |
| tree | 91036c8f6e309c90cb732b3b54d29249388315bc /target | |
| parent | f9911e1e5513ebf661ae871ae31269a9a1cfabdc (diff) | |
target/ppc: 405: Instruction storage interrupt cleanup
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : Fixed removal which was done in the wrong routine ]
Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/excp_helper.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index deba12f4f3..7d89bd0651 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -469,7 +469,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; case POWERPC_EXCP_ISI: /* Instruction storage exception */ trace_ppc_excp_isi(msr, env->nip); - msr |= env->error_code; break; case POWERPC_EXCP_EXTERNAL: /* External input */ break; |