diff options
| author | Changbin Du <changbin.du@gmail.com> | 2020-03-28 22:02:32 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-30 13:55:32 +0100 |
| commit | 88828bf133b64b7a860c166af3423ef1a47c5d3b (patch) | |
| tree | 1cc829aeb1cf7b6170aba2d281edba81bef89166 /target | |
| parent | 660b4e70422bd19b09fa979733645ad6a55d88f2 (diff) | |
target/arm: fix incorrect current EL bug in aarch32 exception emulation
The arm_current_el() should be invoked after mode switching. Otherwise, we
get a wrong current EL value, since current EL is also determined by
current mode.
Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200328140232.17278-1-changbin.du@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index b7b6887241..163c91a1cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); - new_el = arm_current_el(env); /* * For exceptions taken to AArch32 we must clear the SS bit in both @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el = arm_current_el(env); + /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |