diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 07:57:14 -0700 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 07:57:14 -0700 |
commit | 57c9363c452af64fe058aa946cc923eae7f7ad33 (patch) | |
tree | 0889bd686e16e051086b88922ada640376173dc7 /target | |
parent | ca127b3fc247517ec7d4dad291f2c0f90602ce5b (diff) | |
parent | ca5765c8521b8284b8277ed4b811ac0ab9010fc8 (diff) |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* prepare to expand usage of test venv
* fix CPUID when passing through host cache information
* a20 fix
* SGX fix
* generate per-target modinfo
* replay cleanups and simplifications
* "make modules" target
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# gpg: Signature made Mon 06 Jun 2022 07:04:13 AM PDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (29 commits)
meson: qga: do not use deprecated meson.build_root()
configure: remove reference to removed option
regenerate meson-buildoptions.sh
tests: run 'device-crash-test' from tests/venv
tests: add python3-venv to debian10.docker
tests: use tests/venv to run basevm.py-based scripts
tests: install "qemu" namespace package into venv
tests: add quiet-venv-pip macro
tests: silence pip upgrade warnings during venv creation
tests: use python3 as the python executable name
tests: add "TESTS_PYTHON" variable to Makefile
python: update for mypy 0.950
x86: cpu: fixup number of addressable IDs for logical processors sharing cache
x86: cpu: make sure number of addressable IDs for processor cores meets the spec
tests/Makefile.include: Fix 'make check-help' output
tests/avocado: add replay Linux test for Aarch64 machines
tests/avocado: add replay Linux tests for virtio machine
tests/avocado: update replay_linux test
docs: move replay docs to docs/system/replay.rst
docs: convert docs/devel/replay page to rst
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/i386/cpu.c | 22 | ||||
-rw-r--r-- | target/i386/tcg/sysemu/excp_helper.c | 4 |
2 files changed, 20 insertions, 6 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bb6a5dd498..6a57ef13af 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5284,10 +5284,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); - /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ - *eax &= ~0xFC000000; - if ((*eax & 31) && cs->nr_cores > 1) { - *eax |= (cs->nr_cores - 1) << 26; + /* + * QEMU has its own number of cores/logical cpus, + * set 24..14, 31..26 bit to configured values + */ + if (*eax & 31) { + int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); + int vcpus_per_socket = env->nr_dies * cs->nr_cores * + cs->nr_threads; + if (cs->nr_cores > 1) { + *eax &= ~0xFC000000; + *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; + } + if (host_vcpus_per_cache > vcpus_per_socket) { + *eax &= ~0x3FFC000; + *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; + } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax = *ebx = *ecx = *edx = 0; @@ -5559,7 +5571,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, * supports. Features can be further restricted by userspace, but not * made more permissive. */ - x86_cpu_get_supported_cpuid(0x12, index, eax, ebx, ecx, edx); + x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); if (count == 0) { *eax &= env->features[FEAT_SGX_12_0_EAX]; diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index e1b6d88683..48feba7e75 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -359,6 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, CPUX86State *env = &cpu->env; int error_code = PG_ERROR_OK; int pg_mode, prot, page_size; + int32_t a20_mask; hwaddr paddr; hwaddr vaddr; @@ -368,7 +369,8 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, #endif if (!(env->cr[0] & CR0_PG_MASK)) { - paddr = addr; + a20_mask = x86_get_a20_mask(env); + paddr = addr & a20_mask; #ifdef TARGET_X86_64 if (!(env->hflags & HF_LMA_MASK)) { /* Without long mode we can only address 32bits in real mode */ |