diff options
| author | Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | 2024-05-26 13:45:51 -0700 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-06-01 07:20:31 +0300 |
| commit | e08fbea661016a3eefad71eff6ad1aec2d558730 (patch) | |
| tree | 532c3ad55110b89bd0efa366ee9c3c5aa26977fe /target | |
| parent | eed21e9574a2faac4f727e3f6f180ecb03ba1cf1 (diff) | |
target/arm: Disable SVE extensions when SVE is disabled
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240526204551.553282-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit daf9748ac002ec35258e5986b6257961fd04b565)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu64.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3d74f134f5..037e9d9feb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -190,7 +190,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * No explicit bits enabled, and no implicit bits from sve-max-vq. */ if (!cpu_isar_feature(aa64_sve, cpu)) { - /* SVE is disabled and so are all vector lengths. Good. */ + /* + * SVE is disabled and so are all vector lengths. Good. + * Disable all SVE extensions as well. + */ + cpu->isar.id_aa64zfr0 = 0; return; } |