diff options
| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-04-30 13:10:19 +0200 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-05-04 09:37:20 +0300 |
| commit | 07d46408cb9837c54a449d56c9af1b6a2d69ec60 (patch) | |
| tree | ceb56aeda7a27af620492354baec38a6777b7ce9 /target | |
| parent | dc5390a0ca23e3811f793fe15b40ba2a47c4729b (diff) | |
target/sh4: Fix SUBV opcode
The documentation says:
SUBV Rm, Rn Rn - Rm -> Rn, underflow -> T
The overflow / underflow can be calculated as:
T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31
However we were using the incorrect:
T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31
Fix by using the Rn register instead of Rm.
Add tests provided by Paul Cercueil.
Cc: qemu-stable@nongnu.org
Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG")
Reported-by: Paul Cercueil <paul@crapouillou.net>
Suggested-by: Paul Cercueil <paul@crapouillou.net>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2318
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20240430163125.77430-3-philmd@linaro.org>
(cherry picked from commit e88a856efd1d3c3ffa8e53da4831eff8da290808)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sh4/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index d8dcfc3a20..5c0a4cce7a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -934,7 +934,7 @@ static void _decode_opc(DisasContext * ctx) t0 = tcg_temp_new(); tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4)); t1 = tcg_temp_new(); - tcg_gen_xor_i32(t1, t0, REG(B7_4)); + tcg_gen_xor_i32(t1, t0, REG(B11_8)); t2 = tcg_temp_new(); tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); tcg_gen_and_i32(t1, t1, t2); |