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authorPeter Maydell <peter.maydell@linaro.org>2019-02-22 11:26:17 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-22 11:26:17 +0000
commit98e139bcec7544e2ee66117bd52bbec048fa7e4e (patch)
tree3c75b5d5504992548637c52612f31c97563e8014 /target
parentfaf840a359edb53485bc710fbb3adca9498655dd (diff)
parentfb1b0fcc03b0c15bc3580309738280ad9565b6d9 (diff)
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-21-2019-v2' into staging
MIPS queue for February 21st, 2019, v2 # gpg: Signature made Thu 21 Feb 2019 18:37:04 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-21-2019-v2: target/mips: fulong2e: Dynamically generate SPD EEPROM data target/mips: fulong2e: Fix bios flash size hw/pci-host/bonito.c: Add PCI mem region mapped at the correct address target/mips: implement QMP query-cpu-definitions command tests/tcg: target/mips: Add wrappers for MSA integer compare instructions tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count' tests/tcg: target/mips: Correct path to headers in some test source files hw/misc: mips_itu: Fix 32/64 bit issue in a line involving shift operator Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/mips/helper.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 944f094566..c44cdca3b5 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -24,6 +24,7 @@
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "hw/mips/cpudevs.h"
+#include "qapi/qapi-commands-target.h"
enum {
TLBRET_XI = -6,
@@ -1470,3 +1471,35 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
cpu_loop_exit_restore(cs, pc);
}
+
+static void mips_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfoList *entry;
+ CpuDefinitionInfo *info;
+ const char *typename;
+
+ typename = object_class_get_name(oc);
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_MIPS_CPU));
+ info->q_typename = g_strdup(typename);
+
+ entry = g_malloc0(sizeof(*entry));
+ entry->value = info;
+ entry->next = *cpu_list;
+ *cpu_list = entry;
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list;
+
+ list = object_class_get_list(TYPE_MIPS_CPU, false);
+ g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}