diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2018-11-08 13:06:27 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-11-13 15:12:15 -0800 |
| commit | 40cf6a54c92c475cb2f575561fe67044904c16b7 (patch) | |
| tree | 8382fcac689001ee52aa725fb19b321af5ca6b17 /target | |
| parent | 632fb2792b558219146eb48b3a8ee5b53026b3e5 (diff) | |
target/riscv: Fix FCLASS_D being treated as RV64 only
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..5359088e24 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); break; -#if defined(TARGET_RISCV64) case OPC_RISC_FMV_X_D: /* also OPC_RISC_FCLASS_D */ switch (rm) { +#if defined(TARGET_RISCV64) case 0: /* FMV */ gen_set_gpr(rd, cpu_fpr[rs1]); break; +#endif case 1: t0 = tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[rs1]); @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } break; +#if defined(TARGET_RISCV64) case OPC_RISC_FMV_D_X: t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); |