diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-27 11:18:02 -0700 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-30 17:05:07 +0100 |
commit | 9aa60c83ea424036469076cfb2989fe85969673e (patch) | |
tree | af325fd4c2b1c1b672ec46a6937dec6413454b8e /target | |
parent | 6687d05dc318aed9dbd1fc724bcfcbea1a48809a (diff) |
target/arm: Use TRANS_FEAT for do_index
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-50-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/arm/translate-sve.c | 35 |
1 files changed, 8 insertions, 27 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 44c2342923..dac29749ce 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1126,33 +1126,14 @@ static bool do_index(DisasContext *s, int esz, int rd, return true; } -static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) -{ - TCGv_i64 start = tcg_constant_i64(a->imm1); - TCGv_i64 incr = tcg_constant_i64(a->imm2); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) -{ - TCGv_i64 start = tcg_constant_i64(a->imm); - TCGv_i64 incr = cpu_reg(s, a->rm); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) -{ - TCGv_i64 start = cpu_reg(s, a->rn); - TCGv_i64 incr = tcg_constant_i64(a->imm); - return do_index(s, a->esz, a->rd, start, incr); -} - -static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) -{ - TCGv_i64 start = cpu_reg(s, a->rn); - TCGv_i64 incr = cpu_reg(s, a->rm); - return do_index(s, a->esz, a->rd, start, incr); -} +TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd, + tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2)) +TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd, + tcg_constant_i64(a->imm), cpu_reg(s, a->rm)) +TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd, + cpu_reg(s, a->rn), tcg_constant_i64(a->imm)) +TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd, + cpu_reg(s, a->rn), cpu_reg(s, a->rm)) /* *** SVE Stack Allocation Group |