diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-27 11:17:48 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-30 17:05:06 +0100 |
| commit | 2aa469ff5fde3f1c59b14ddf48d58018e2f03982 (patch) | |
| tree | 33514db1072986f9bf01428ec1ed160d2f1bbf4b /target | |
| parent | 79828dcbf5a497e83d350a2f8f8e61429fc60c89 (diff) | |
target/arm: Use TRANS_FEAT for RAX1
The decode for RAX1 sets esz to MO_8, because that's what
we use by default for "no esz present". We changed that
to MO_64 during translation because it is more logical for
the operation. However, the esz argument to gen_gvec_rax1
is unused and forces MO_64 within that function, so there
is no need to do it here as well.
Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-36-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-sve.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e92fef2304..36d739d7b2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7814,13 +7814,7 @@ TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) -static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a) -{ - if (!dc_isar_feature(aa64_sve2_sha3, s)) { - return false; - } - return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm); -} +TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) { |