diff options
| author | Fredrik Noring <noring@nocrew.org> | 2019-01-17 18:44:05 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-01-18 16:53:28 +0100 |
| commit | a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd (patch) | |
| tree | 3ce5635f8ee58d3e45ee71d21c1c325d62a7020b /target | |
| parent | 294fc2ea7f8af913523bf004433704377d9ee7a8 (diff) | |
target/mips: Introduce 32 R5900 multimedia registers
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/cpu.h | 3 | ||||
| -rw-r--r-- | target/mips/translate.c | 16 |
2 files changed, 19 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21daf501ce..c4da7dfbfd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -429,6 +429,9 @@ struct TCState { float_status msa_fp_status; + /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ + uint64_t mmr[32]; + #define NUMBER_OF_MXU_REGISTERS 16 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; target_ulong mxu_cr; diff --git a/target/mips/translate.c b/target/mips/translate.c index 3ac0b1fdbd..ab307c410c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2455,6 +2455,11 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +#if defined(TARGET_MIPS64) +/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */ +static TCGv_i64 cpu_mmr[32]; +#endif + #if !defined(TARGET_MIPS64) /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; @@ -29845,6 +29850,17 @@ void mips_tcg_init(void) fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); + +#if defined(TARGET_MIPS64) + cpu_mmr[0] = NULL; + for (i = 1; i < 32; i++) { + cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUMIPSState, + active_tc.mmr[i]), + regnames[i]); + } +#endif + #if !defined(TARGET_MIPS64) for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] = tcg_global_mem_new(cpu_env, |