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authorPeter Maydell <peter.maydell@linaro.org>2019-03-28 08:00:22 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-03-28 08:00:22 +0000
commit2fc8d6f8e4d959b05e9225b46dad414bd8f54f88 (patch)
tree3b72a602fea627166c83c740ee8f37b70cfbdc91 /target
parent49fc899f8d673dd9e73f3db0d9e9ea60b77c331b (diff)
parentbc19449acc2e05854118a47cdf96c1e86b30740d (diff)
Merge remote-tracking branch 'remotes/xtensa/tags/20190326-xtensa' into staging
target/xtensa fixes for v4.0: - fix translation of FLIX bundles with multiple references to the same register; - don't announce exit simcall; - clean up tests/tcg/xtensa. # gpg: Signature made Tue 26 Mar 2019 17:58:59 GMT # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190326-xtensa: tests/tcg/xtensa: clean up test set target/xtensa: don't announce exit simcall target/xtensa: fix break_dependency for repeated resources Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/xtensa/translate.c1
-rw-r--r--target/xtensa/xtensa-semi.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 77bc04d6b0..65561d2c49 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1041,7 +1041,6 @@ static bool break_dependency(struct slot_prop *a,
copy[n].resource = b->in[j].resource;
copy[n].arg = b->arg + index;
++n;
- ++i;
++j;
rv = true;
}
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index 2f76216276..5f5ce4f344 100644
--- a/target/xtensa/xtensa-semi.c
+++ b/target/xtensa/xtensa-semi.c
@@ -202,7 +202,6 @@ void HELPER(simcall)(CPUXtensaState *env)
switch (regs[2]) {
case TARGET_SYS_exit:
- qemu_log("exit(%d) simcall\n", regs[3]);
exit(regs[3]);
break;