diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2017-05-01 23:20:43 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-05-13 11:18:26 +0200 |
| commit | a380f9db96dc94e5109611e4fd0fb4f671e30143 (patch) | |
| tree | 7ef41df51ce6e938438abf473cba3865cbf6910f /target | |
| parent | 58d2a9aef4cacb3056f5b12c1eb92105704183fe (diff) | |
target/sh4: optimize gen_write_sr using extract op
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sh4/translate.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index fe8bff54a6..7a504a7f5a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) { tcg_gen_andi_i32(cpu_sr, src, ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); } static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) |