diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-09-03 14:32:08 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-14 14:23:19 +0100 |
| commit | 0ae715c658a02af1834b63563c56112a6d8842cb (patch) | |
| tree | 9c53cddc134d19e2e4e7b3dd88e207da92f03f96 /target | |
| parent | 6cf0f240e0b980a877abed12d2995f740eae6515 (diff) | |
target/arm: Convert Neon VCVT fp size field to MO_* in decode
Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats
to pass the size through to the trans function as a MO_* value
rather than the '0==f32, 1==f16' used in the fp 3-same encodings.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-3-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/neon-dp.decode | 3 | ||||
| -rw-r--r-- | target/arm/translate-neon.c.inc | 4 |
2 files changed, 3 insertions, 4 deletions
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index ea2f0dfcf1..51aa0f0819 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -256,9 +256,8 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp @2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \ &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0 -# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings. @2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \ - &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5 + &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5 @2reg_vcvt_f16 .... ... . . . 11 .... .... .... . q:1 . . .... \ &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 255c1cf8a2..213c1c2174 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -1626,7 +1626,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, return false; } - if (a->size != 0) { + if (a->size == MO_16) { if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -1646,7 +1646,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, return true; } - fpst = fpstatus_ptr(a->size ? FPST_STD_F16 : FPST_STD); + fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift, fn); tcg_temp_free_ptr(fpst); return true; |