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authorFrank Chang <frank.chang@sifive.com>2021-05-06 00:06:13 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-06-08 09:59:45 +1000
commit831ec7f3d1ede387eca225ccaccb2845cbbca85e (patch)
tree5a06a79165f54f1c0e7bd5833f41d531dc005479 /target
parente58529a8d03ab8e9127f3e7cdf757ff84af75698 (diff)
target/riscv: rvb: generalized reverse
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210505160620.15723-13-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/bitmanip_helper.c64
-rw-r--r--target/riscv/helper.h4
-rw-r--r--target/riscv/insn32.decode4
-rw-r--r--target/riscv/insn_trans/trans_rvb.c.inc31
-rw-r--r--target/riscv/meson.build1
-rw-r--r--target/riscv/translate.c28
6 files changed, 132 insertions, 0 deletions
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 0000000000..c625adaded
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,64 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+ dup_const(MO_8, 0x55),
+ dup_const(MO_8, 0x33),
+ dup_const(MO_8, 0x0f),
+ dup_const(MO_16, 0xff),
+ dup_const(MO_32, 0xffff),
+ UINT32_MAX
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x = do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7267593c3..f81b8faf3b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -58,6 +58,10 @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 71a9a182c0..6b5e276a9f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -684,6 +684,7 @@ slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
+grev 0110100 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -692,6 +693,7 @@ bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
+grevi 01101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -708,6 +710,7 @@ slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
+grevw 0110100 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -715,3 +718,4 @@ binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
+greviw 0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 429738db15..281e0ffae9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -197,6 +197,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, tcg_gen_rotl_tl);
}
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_grevi(ctx, a);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -329,3 +346,17 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftw(ctx, a, gen_rolw);
}
+
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_grevw);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index af6c3416b7..d5e0bc93ea 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -16,6 +16,7 @@ riscv_ss.add(files(
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
+ 'bitmanip_helper.c',
'translate.c',
))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c09b93f1b8..8deb05add4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -627,6 +627,28 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2;
+
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
+ /* rev8, byte swaps */
+ tcg_gen_bswap_tl(source1, source1);
+ } else {
+ source2 = tcg_temp_new();
+ tcg_gen_movi_tl(source2, a->shamt);
+ gen_helper_grev(source1, source1, source2);
+ tcg_temp_free(source2);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -699,6 +721,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_grev(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{