diff options
author | Kito Cheng <kito.cheng@sifive.com> | 2021-05-06 00:06:05 +0800 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:44 +1000 |
commit | 0bcdb686e586d8f5bfa2b2f9261d75a76b15e3cb (patch) | |
tree | 93de82039d6622e3e88b7b0da5559b9fa4dce239 /target | |
parent | 1e16310ca1bd368f20eb93683cc37389d5db185d (diff) |
target/riscv: rvb: logic-with-negate
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/riscv/insn32.decode | 3 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 18 |
2 files changed, 21 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f7671872d..a4d95ea621 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 cpop 011000 000010 ..... 001 ..... 0010011 @r2 +andn 0100000 .......... 111 ..... 0110011 @r +orn 0100000 .......... 110 ..... 0110011 @r +xnor 0100000 .......... 100 ..... 0110011 @r # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 4a5d271b43..b8676785c6 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a) return gen_unary(ctx, a, tcg_gen_ctpop_tl); } +static bool trans_andn(DisasContext *ctx, arg_andn *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, tcg_gen_andc_tl); +} + +static bool trans_orn(DisasContext *ctx, arg_orn *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, tcg_gen_orc_tl); +} + +static bool trans_xnor(DisasContext *ctx, arg_xnor *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, tcg_gen_eqv_tl); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); |