Merge remote-tracking branch 'remotes/xtensa/tags/20181001-xtensa' into staging

target/xtensa: preparation for FLIX support

Separate generation of per-instruction code (such as raising exceptions
and terminating TB) from per-opcode code.

# gpg: Signature made Mon 01 Oct 2018 19:14:34 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20181001-xtensa:
  target/xtensa: extract gen_check_interrupts call
  target/xtensa: make rsr/wsr helpers return void
  target/xtensa: extract unconditional TB termination via slot 0
  target/xtensa: always end TB on CCOUNT access/CCOMPARE write
  target/xtensa: change SR number checks to assertions
  target/xtensa: extract unconditional TB termination
  target/xtensa: extract test for division by zero
  target/xtensa: extract test for cpdisabled exception
  target/xtensa: extract test for alloca exception
  target/xtensa: extract test for window underflow exception
  target/xtensa: extract test for window overflow exception
  target/xtensa: extract test for debug exception
  target/xtensa: extract test for syscall instruction
  target/xtensa: extract test for privileged instruction
  target/xtensa: extract test for an illegal instruction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

5 files changed, 1816 insertions, 973 deletions

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 1362772617..34e5ccd9f1 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -217,6 +217,7 @@ enum {
 #define MEMCTL_IL0EN 0x1
 
 #define MAX_INSN_LENGTH 64
+#define MAX_INSN_SLOTS 32
 #define MAX_OPCODE_ARGS 16
 #define MAX_NAREG 64
 #define MAX_NINTERRUPT 32
@@ -347,11 +348,40 @@ typedef struct XtensaMemory {
 typedef struct DisasContext DisasContext;
 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
                                const uint32_t par[]);
+typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
+                                     const uint32_t arg[],
+                                     const uint32_t par[]);
+typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
+                                         const uint32_t arg[],
+                                         const uint32_t par[]);
+
+enum {
+    XTENSA_OP_ILL = 0x1,
+    XTENSA_OP_PRIVILEGED = 0x2,
+    XTENSA_OP_SYSCALL = 0x4,
+    XTENSA_OP_DEBUG_BREAK = 0x8,
+
+    XTENSA_OP_OVERFLOW = 0x10,
+    XTENSA_OP_UNDERFLOW = 0x20,
+    XTENSA_OP_ALLOCA = 0x40,
+    XTENSA_OP_COPROCESSOR = 0x80,
+
+    XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
+
+    XTENSA_OP_CHECK_INTERRUPTS = 0x200,
+    XTENSA_OP_EXIT_TB_M1 = 0x400,
+    XTENSA_OP_EXIT_TB_0 = 0x800,
+};
 
 typedef struct XtensaOpcodeOps {
     const char *name;
     XtensaOpcodeOp translate;
+    XtensaOpcodeBoolTest test_ill;
+    XtensaOpcodeUintTest test_overflow;
     const uint32_t *par;
+    uint32_t op_flags;
+    uint32_t windowed_register_op;
+    uint32_t coprocessor;
 } XtensaOpcodeOps;
 
 typedef struct XtensaOpcodeTranslators {
@@ -661,6 +691,9 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
 #define XTENSA_TBFLAG_YIELD 0x20000
+#define XTENSA_TBFLAG_CWOE 0x40000
+#define XTENSA_TBFLAG_CALLINC_MASK 0x180000
+#define XTENSA_TBFLAG_CALLINC_SHIFT 19
 
 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
         target_ulong *cs_base, uint32_t *flags)
@@ -698,7 +731,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
             (env->sregs[WINDOW_BASE] + 1);
         uint32_t w = ctz32(windowstart | 0x8);
 
-        *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
+        *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+        *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+                            PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
     } else {
         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
     }
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 4fceb4424a..501082f55b 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -57,12 +57,18 @@ static void init_libisa(XtensaConfig *config)
 {
     unsigned i, j;
     unsigned opcodes;
+    unsigned formats;
 
     config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
     assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
     opcodes = xtensa_isa_num_opcodes(config->isa);
+    formats = xtensa_isa_num_formats(config->isa);
     config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
 
+    for (i = 0; i < formats; ++i) {
+        assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS);
+    }
+
     for (i = 0; i < opcodes; ++i) {
         const char *opc_name = xtensa_opcode_name(config->isa, i);
         XtensaOpcodeOps *ops = NULL;
diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h
index 73444ae02c..10153c2453 100644
--- a/target/xtensa/helper.h
+++ b/target/xtensa/helper.h
@@ -5,6 +5,8 @@ DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
 
 DEF_HELPER_2(wsr_windowbase, void, env, i32)
 DEF_HELPER_4(entry, void, env, i32, i32, i32)
+DEF_HELPER_2(test_ill_retw, void, env, i32)
+DEF_HELPER_2(test_underflow_retw, void, env, i32)
 DEF_HELPER_2(retw, i32, env, i32)
 DEF_HELPER_2(rotw, void, env, i32)
 DEF_HELPER_3(window_check, noreturn, env, i32, i32)
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index 06fe346f02..e4b42ab3e5 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -253,22 +253,11 @@ void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
 {
     int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
-    if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
-        qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n",
-                      pc, env->sregs[PS]);
-        HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
-    } else {
-        uint32_t windowstart = xtensa_replicate_windowstart(env) >>
-            (env->sregs[WINDOW_BASE] + 1);
 
-        if (windowstart & ((1 << callinc) - 1)) {
-            HELPER(window_check)(env, pc, callinc);
-        }
-        env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
-        xtensa_rotate_window(env, callinc);
-        env->sregs[WINDOW_START] |=
-            windowstart_bit(env->sregs[WINDOW_BASE], env);
-    }
+    env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
+    xtensa_rotate_window(env, callinc);
+    env->sregs[WINDOW_START] |=
+        windowstart_bit(env->sregs[WINDOW_BASE], env);
 }
 
 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
@@ -298,13 +287,12 @@ void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
     }
 }
 
-uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
+void HELPER(test_ill_retw)(CPUXtensaState *env, uint32_t pc)
 {
     int n = (env->regs[0] >> 30) & 0x3;
     int m = 0;
     uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
     uint32_t windowstart = env->sregs[WINDOW_START];
-    uint32_t ret_pc = 0;
 
     if (windowstart & windowstart_bit(windowbase - 1, env)) {
         m = 1;
@@ -314,35 +302,46 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
         m = 3;
     }
 
-    if (n == 0 || (m != 0 && m != n) ||
-            ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
+    if (n == 0 || (m != 0 && m != n)) {
         qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
                       "PS = %08x, m = %d, n = %d\n",
                       pc, env->sregs[PS], m, n);
         HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
-    } else {
-        int owb = windowbase;
+    }
+}
+
+void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc)
+{
+    int n = (env->regs[0] >> 30) & 0x3;
 
-        ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
+    if (!(env->sregs[WINDOW_START] &
+          windowstart_bit(env->sregs[WINDOW_BASE] - n, env))) {
+        uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
 
         xtensa_rotate_window(env, -n);
-        if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
-            env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
-        } else {
-            /* window underflow */
-            env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
-                (windowbase << PS_OWB_SHIFT) | PS_EXCM;
-            env->sregs[EPC1] = env->pc = pc;
-
-            if (n == 1) {
-                HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
-            } else if (n == 2) {
-                HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
-            } else if (n == 3) {
-                HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
-            }
+        /* window underflow */
+        env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
+            (windowbase << PS_OWB_SHIFT) | PS_EXCM;
+        env->sregs[EPC1] = env->pc = pc;
+
+        if (n == 1) {
+            HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
+        } else if (n == 2) {
+            HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
+        } else if (n == 3) {
+            HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
         }
     }
+}
+
+uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
+{
+    int n = (env->regs[0] >> 30) & 0x3;
+    uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
+    uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
+
+    xtensa_rotate_window(env, -n);
+    env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env);
     return ret_pc;
 }
 
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index c626583cd9..46e1338448 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -62,6 +62,8 @@ struct DisasContext {
     TCGv_i32 sar_m32;
 
     unsigned window;
+    unsigned callinc;
+    bool cwoe;
 
     bool debug;
     bool icount;
@@ -349,11 +351,12 @@ static bool gen_check_privilege(DisasContext *dc)
     return false;
 }
 
-static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
+static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
 {
-    if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
-            !(dc->cpenable & (1 << cp))) {
-        gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
+    cp_mask &= ~dc->cpenable;
+
+    if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
+        gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
         dc->base.is_jmp = DISAS_NORETURN;
         return false;
     }
@@ -469,7 +472,7 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond,
     tcg_temp_free(tmp);
 }
 
-static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
+static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access)
 {
     if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
         if (sregnames[sr].name) {
@@ -477,7 +480,6 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
         } else {
             qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
         }
-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
         return false;
     } else if (!(sregnames[sr].access & access)) {
         static const char * const access_text[] = {
@@ -488,14 +490,13 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
         assert(access < ARRAY_SIZE(access_text) && access_text[access]);
         qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
                       access_text[access]);
-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
         return false;
     }
     return true;
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
+static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 {
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_start();
@@ -504,24 +505,21 @@ static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
     tcg_gen_mov_i32(d, cpu_SR[sr]);
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_end();
-        return true;
     }
-    return false;
 }
 
-static bool gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
+static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 {
     tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
     tcg_gen_or_i32(d, d, cpu_SR[sr]);
     tcg_gen_andi_i32(d, d, 0xfffffffc);
-    return false;
 }
 #endif
 
-static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
+static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 {
-    static bool (* const rsr_handler[256])(DisasContext *dc,
-            TCGv_i32 d, uint32_t sr) = {
+    static void (* const rsr_handler[256])(DisasContext *dc,
+                                           TCGv_i32 d, uint32_t sr) = {
 #ifndef CONFIG_USER_ONLY
         [CCOUNT] = gen_rsr_ccount,
         [INTSET] = gen_rsr_ccount,
@@ -530,28 +528,23 @@ static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
     };
 
     if (rsr_handler[sr]) {
-        return rsr_handler[sr](dc, d, sr);
+        rsr_handler[sr](dc, d, sr);
     } else {
         tcg_gen_mov_i32(d, cpu_SR[sr]);
-        return false;
     }
 }
 
-static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     gen_helper_wsr_lbeg(cpu_env, s);
-    gen_jumpi_check_loop_end(dc, 0);
-    return false;
 }
 
-static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     gen_helper_wsr_lend(cpu_env, s);
-    gen_jumpi_check_loop_end(dc, 0);
-    return false;
 }
 
-static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
     if (dc->sar_m32_5bit) {
@@ -559,129 +552,97 @@ static bool gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
     }
     dc->sar_5bit = false;
     dc->sar_m32_5bit = false;
-    return false;
 }
 
-static bool gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
-    return false;
 }
 
-static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
     tcg_gen_ext8s_i32(cpu_SR[sr], s);
-    return false;
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     gen_helper_wsr_windowbase(cpu_env, v);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
-    return false;
 }
 
-static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     gen_helper_wsr_rasid(cpu_env, v);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
-    return false;
 }
 
-static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     gen_helper_wsr_ibreakenable(cpu_env, v);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
 }
 
-static bool gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     gen_helper_wsr_memctl(cpu_env, v);
-    return false;
 }
 
-static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
-    return false;
 }
 
-static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     unsigned id = sr - IBREAKA;
+    TCGv_i32 tmp = tcg_const_i32(id);
 
-    if (id < dc->config->nibreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_ibreaka(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
-        gen_jumpi_check_loop_end(dc, 0);
-        return true;
-    }
-    return false;
+    assert(id < dc->config->nibreak);
+    gen_helper_wsr_ibreaka(cpu_env, tmp, v);
+    tcg_temp_free(tmp);
 }
 
-static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     unsigned id = sr - DBREAKA;
+    TCGv_i32 tmp = tcg_const_i32(id);
 
-    if (id < dc->config->ndbreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_dbreaka(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
-    }
-    return false;
+    assert(id < dc->config->ndbreak);
+    gen_helper_wsr_dbreaka(cpu_env, tmp, v);
+    tcg_temp_free(tmp);
 }
 
-static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     unsigned id = sr - DBREAKC;
+    TCGv_i32 tmp = tcg_const_i32(id);
 
-    if (id < dc->config->ndbreak) {
-        TCGv_i32 tmp = tcg_const_i32(id);
-        gen_helper_wsr_dbreakc(cpu_env, tmp, v);
-        tcg_temp_free(tmp);
-    }
-    return false;
+    assert(id < dc->config->ndbreak);
+    gen_helper_wsr_dbreakc(cpu_env, tmp, v);
+    tcg_temp_free(tmp);
 }
 
-static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
 static void gen_check_interrupts(DisasContext *dc)
@@ -695,16 +656,13 @@ static void gen_check_interrupts(DisasContext *dc)
     }
 }
 
-static bool gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v,
             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
 }
 
-static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
 
@@ -714,20 +672,14 @@ static bool gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
     tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
     tcg_temp_free(tmp);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
 }
 
-static bool gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_mov_i32(cpu_SR[sr], v);
-    gen_check_interrupts(dc);
-    gen_jumpi_check_loop_end(dc, 0);
-    return true;
 }
 
-static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
         PS_UM | PS_EXCM | PS_INTLEVEL;
@@ -736,13 +688,9 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
         mask |= PS_RING;
     }
     tcg_gen_andi_i32(cpu_SR[sr], v, mask);
-    gen_check_interrupts(dc);
-    /* This can change mmu index and tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_start();
@@ -750,53 +698,40 @@ static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
     gen_helper_wsr_ccount(cpu_env, v);
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_end();
-        gen_jumpi_check_loop_end(dc, 0);
-        return true;
     }
-    return false;
 }
 
-static bool gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     if (dc->icount) {
         tcg_gen_mov_i32(dc->next_icount, v);
     } else {
         tcg_gen_mov_i32(cpu_SR[sr], v);
     }
-    return false;
 }
 
-static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
-    return true;
 }
 
-static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
     uint32_t id = sr - CCOMPARE;
-    bool ret = false;
+    uint32_t int_bit = 1 << dc->config->timerint[id];
+    TCGv_i32 tmp = tcg_const_i32(id);
 
-    if (id < dc->config->nccompare) {
-        uint32_t int_bit = 1 << dc->config->timerint[id];
-        TCGv_i32 tmp = tcg_const_i32(id);
-
-        tcg_gen_mov_i32(cpu_SR[sr], v);
-        tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
-        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-            gen_io_start();
-        }
-        gen_helper_update_ccompare(cpu_env, tmp);
-        if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-            gen_io_end();
-            gen_jumpi_check_loop_end(dc, 0);
-            ret = true;
-        }
-        tcg_temp_free(tmp);
+    assert(id < dc->config->nccompare);
+    tcg_gen_mov_i32(cpu_SR[sr], v);
+    tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_update_ccompare(cpu_env, tmp);
+    tcg_temp_free(tmp);
+    if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+        gen_io_end();
     }
-    return ret;
 }
 #else
 static void gen_check_interrupts(DisasContext *dc)
@@ -804,10 +739,10 @@ static void gen_check_interrupts(DisasContext *dc)
 }
 #endif
 
-static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 {
-    static bool (* const wsr_handler[256])(DisasContext *dc,
-            uint32_t sr, TCGv_i32 v) = {
+    static void (* const wsr_handler[256])(DisasContext *dc,
+                                           uint32_t sr, TCGv_i32 v) = {
         [LBEG] = gen_wsr_lbeg,
         [LEND] = gen_wsr_lend,
         [SAR] = gen_wsr_sar,
@@ -845,10 +780,9 @@ static bool gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
     };
 
     if (wsr_handler[sr]) {
-        return wsr_handler[sr](dc, sr, s);
+        wsr_handler[sr](dc, sr, s);
     } else {
         tcg_gen_mov_i32(cpu_SR[sr], s);
-        return false;
     }
 }
 
@@ -901,15 +835,16 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4)
     }
     tcg_temp_free(pc);
     tcg_temp_free(intlevel);
-    gen_jumpi_check_loop_end(dc, 0);
 }
 #endif
 
-static bool gen_window_check1(DisasContext *dc, unsigned r1)
+static bool gen_window_check(DisasContext *dc, uint32_t mask)
 {
-    if (r1 / 4 > dc->window) {
+    unsigned r = 31 - clz32(mask);
+
+    if (r / 4 > dc->window) {
         TCGv_i32 pc = tcg_const_i32(dc->pc);
-        TCGv_i32 w = tcg_const_i32(r1 / 4);
+        TCGv_i32 w = tcg_const_i32(r / 4);
 
         gen_helper_window_check(cpu_env, pc, w);
         dc->base.is_jmp = DISAS_NORETURN;
@@ -918,17 +853,6 @@ static bool gen_window_check1(DisasContext *dc, unsigned r1)
     return true;
 }
 
-static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
-{
-    return gen_window_check1(dc, r1 > r2 ? r1 : r2);
-}
-
-static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
-        unsigned r3)
-{
-    return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
-}
-
 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
 {
     TCGv_i32 m = tcg_temp_new_i32();
@@ -941,6 +865,15 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
     return m;
 }
 
+static void gen_zero_check(DisasContext *dc, const uint32_t arg[])
+{
+    TCGLabel *label = gen_new_label();
+
+    tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label);
+    gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
+    gen_set_label(label);
+}
+
 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
 {
     return xtensa_isa_length_from_chars(dc->config->isa, &op0);
@@ -954,6 +887,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
     xtensa_format fmt;
     int slot, slots;
     unsigned i;
+    uint32_t op_flags = 0;
+    struct {
+        XtensaOpcodeOps *ops;
+        uint32_t arg[MAX_OPCODE_ARGS];
+        uint32_t raw_arg[MAX_OPCODE_ARGS];
+    } slot_prop[MAX_INSN_SLOTS];
+    uint32_t debug_cause = 0;
+    uint32_t windowed_register = 0;
+    uint32_t coprocessor = 0;
 
     if (len == XTENSA_UNDEFINED) {
         qemu_log_mask(LOG_GUEST_ERROR,
@@ -987,8 +929,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
     for (slot = 0; slot < slots; ++slot) {
         xtensa_opcode opc;
         int opnd, vopnd, opnds;
-        uint32_t raw_arg[MAX_OPCODE_ARGS];
-        uint32_t arg[MAX_OPCODE_ARGS];
+        uint32_t *raw_arg = slot_prop[slot].raw_arg;
+        uint32_t *arg = slot_prop[slot].arg;
         XtensaOpcodeOps *ops;
 
         dc->raw_arg = raw_arg;
@@ -1020,16 +962,105 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
             }
         }
         ops = dc->config->opcode_ops[opc];
+        slot_prop[slot].ops = ops;
+
         if (ops) {
-            ops->translate(dc, arg, ops->par);
+            op_flags |= ops->op_flags;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR,
+            qemu_log_mask(LOG_UNIMP,
                           "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
                           xtensa_opcode_name(isa, opc), slot, dc->pc);
+            op_flags |= XTENSA_OP_ILL;
+        }
+        if ((op_flags & XTENSA_OP_ILL) ||
+            (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) {
             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
             return;
         }
+        if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) {
+            debug_cause |= ops->par[0];
+        }
+        if (ops->test_overflow) {
+            windowed_register |= ops->test_overflow(dc, arg, ops->par);
+        }
+        if (ops->windowed_register_op) {
+            uint32_t reg_opnd = ops->windowed_register_op;
+
+            while (reg_opnd) {
+                unsigned i = ctz32(reg_opnd);
+
+                windowed_register |= 1 << arg[i];
+                reg_opnd ^= 1 << i;
+            }
+        }
+        coprocessor |= ops->coprocessor;
+    }
+
+    if ((op_flags & XTENSA_OP_PRIVILEGED) &&
+        !gen_check_privilege(dc)) {
+        return;
+    }
+
+    if (op_flags & XTENSA_OP_SYSCALL) {
+        gen_exception_cause(dc, SYSCALL_CAUSE);
+        return;
+    }
+
+    if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
+        gen_debug_exception(dc, debug_cause);
+        return;
+    }
+
+    if (windowed_register && !gen_window_check(dc, windowed_register)) {
+        return;
+    }
+
+    if (op_flags & XTENSA_OP_UNDERFLOW) {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_test_underflow_retw(cpu_env, tmp);
+        tcg_temp_free(tmp);
+    }
+
+    if (op_flags & XTENSA_OP_ALLOCA) {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_movsp(cpu_env, tmp);
+        tcg_temp_free(tmp);
+    }
+
+    if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
+        return;
+    }
+
+    if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
+        for (slot = 0; slot < slots; ++slot) {
+            if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
+                gen_zero_check(dc, slot_prop[slot].arg);
+            }
+        }
+    }
+
+    for (slot = 0; slot < slots; ++slot) {
+        XtensaOpcodeOps *ops = slot_prop[slot].ops;
+
+        dc->raw_arg = slot_prop[slot].raw_arg;
+        ops->translate(dc, slot_prop[slot].arg, ops->par);
+    }
+
+    if (dc->base.is_jmp == DISAS_NEXT) {
+        if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
+            gen_check_interrupts(dc);
+        }
+
+        if (op_flags & XTENSA_OP_EXIT_TB_M1) {
+            /* Change in mmu index, memory mapping or tb->flags; exit tb */
+            gen_jumpi_check_loop_end(dc, -1);
+        } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
+            gen_jumpi_check_loop_end(dc, 0);
+        }
     }
+
     if (dc->base.is_jmp == DISAS_NEXT) {
         gen_check_loop_end(dc, 0);
     }
@@ -1074,6 +1105,9 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
         XTENSA_TBFLAG_CPENABLE_SHIFT;
     dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
                  XTENSA_TBFLAG_WINDOW_SHIFT);
+    dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
+    dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
+                   XTENSA_TBFLAG_CALLINC_SHIFT);
 
     if (dc->config->isa) {
         dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
@@ -1295,43 +1329,35 @@ xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
 static void translate_abs(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 neg = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 neg = tcg_temp_new_i32();
 
-        tcg_gen_neg_i32(neg, cpu_R[arg[1]]);
-        tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]],
-                            cpu_R[arg[1]], zero, cpu_R[arg[1]], neg);
-        tcg_temp_free(neg);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_neg_i32(neg, cpu_R[arg[1]]);
+    tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]],
+                        cpu_R[arg[1]], zero, cpu_R[arg[1]], neg);
+    tcg_temp_free(neg);
+    tcg_temp_free(zero);
 }
 
 static void translate_add(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_addi(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
 }
 
 static void translate_addx(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
-        tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
+    tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
+    tcg_temp_free(tmp);
 }
 
 static void translate_all(DisasContext *dc, const uint32_t arg[],
@@ -1357,93 +1383,77 @@ static void translate_all(DisasContext *dc, const uint32_t arg[],
 static void translate_and(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_ball(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
-        gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
+    gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]);
+    tcg_temp_free(tmp);
 }
 
 static void translate_bany(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]);
+    gen_brcondi(dc, par[0], tmp, 0, arg[2]);
+    tcg_temp_free(tmp);
 }
 
 static void translate_b(DisasContext *dc, const uint32_t arg[],
                         const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
 }
 
 static void translate_bb(DisasContext *dc, const uint32_t arg[],
                          const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
 #ifdef TARGET_WORDS_BIGENDIAN
-        TCGv_i32 bit = tcg_const_i32(0x80000000u);
+    TCGv_i32 bit = tcg_const_i32(0x80000000u);
 #else
-        TCGv_i32 bit = tcg_const_i32(0x00000001u);
+    TCGv_i32 bit = tcg_const_i32(0x00000001u);
 #endif
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f);
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f);
 #ifdef TARGET_WORDS_BIGENDIAN
-        tcg_gen_shr_i32(bit, bit, tmp);
+    tcg_gen_shr_i32(bit, bit, tmp);
 #else
-        tcg_gen_shl_i32(bit, bit, tmp);
+    tcg_gen_shl_i32(bit, bit, tmp);
 #endif
-        tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit);
-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(bit);
-    }
+    tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit);
+    gen_brcondi(dc, par[0], tmp, 0, arg[2]);
+    tcg_temp_free(tmp);
+    tcg_temp_free(bit);
 }
 
 static void translate_bbi(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp = tcg_temp_new_i32();
 #ifdef TARGET_WORDS_BIGENDIAN
-        tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]);
+    tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]);
 #else
-        tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]);
+    tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]);
 #endif
-        gen_brcondi(dc, par[0], tmp, 0, arg[2]);
-        tcg_temp_free(tmp);
-    }
+    gen_brcondi(dc, par[0], tmp, 0, arg[2]);
+    tcg_temp_free(tmp);
 }
 
 static void translate_bi(DisasContext *dc, const uint32_t arg[],
                          const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]);
-    }
+    gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]);
 }
 
 static void translate_bz(DisasContext *dc, const uint32_t arg[],
                          const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]);
-    }
+    gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]);
 }
 
 enum {
@@ -1486,14 +1496,6 @@ static void translate_bp(DisasContext *dc, const uint32_t arg[],
     tcg_temp_free(tmp);
 }
 
-static void translate_break(DisasContext *dc, const uint32_t arg[],
-                            const uint32_t par[])
-{
-    if (dc->debug) {
-        gen_debug_exception(dc, par[0]);
-    }
-}
-
 static void translate_call0(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
@@ -1501,50 +1503,48 @@ static void translate_call0(DisasContext *dc, const uint32_t arg[],
     gen_jumpi(dc, arg[0], 0);
 }
 
+static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[],
+                                    const uint32_t par[])
+{
+    return 1 << (par[0] * 4);
+}
+
 static void translate_callw(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, par[0] << 2)) {
-        gen_callwi(dc, par[0], arg[0], 0);
-    }
+    gen_callwi(dc, par[0], arg[0], 0);
 }
 
 static void translate_callx0(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
-        gen_jump(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
+    tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
+    gen_jump(dc, tmp);
+    tcg_temp_free(tmp);
 }
 
 static void translate_callxw(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], par[0] << 2)) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp = tcg_temp_new_i32();
 
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        gen_callw(dc, par[0], tmp);
-        tcg_temp_free(tmp);
-    }
+    tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
+    gen_callw(dc, par[0], tmp);
+    tcg_temp_free(tmp);
 }
 
 static void translate_clamps(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]);
-        TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1);
+    TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]);
+    TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1);
 
-        tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]);
-        tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2);
-        tcg_temp_free(tmp1);
-        tcg_temp_free(tmp2);
-    }
+    tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]);
+    tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2);
+    tcg_temp_free(tmp1);
+    tcg_temp_free(tmp2);
 }
 
 static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[],
@@ -1557,39 +1557,49 @@ static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[],
 static void translate_const16(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 c = tcg_const_i32(arg[1]);
+    TCGv_i32 c = tcg_const_i32(arg[1]);
 
-        tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16);
-        tcg_temp_free(c);
-    }
+    tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16);
+    tcg_temp_free(c);
 }
 
-/* par[0]: privileged, par[1]: check memory access */
 static void translate_dcache(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if ((!par[0] || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0]) && par[1]) {
-        TCGv_i32 addr = tcg_temp_new_i32();
-        TCGv_i32 res = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 res = tcg_temp_new_i32();
 
-        tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
-        tcg_gen_qemu_ld8u(res, addr, dc->cring);
-        tcg_temp_free(addr);
-        tcg_temp_free(res);
-    }
+    tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
+    tcg_gen_qemu_ld8u(res, addr, dc->cring);
+    tcg_temp_free(addr);
+    tcg_temp_free(res);
 }
 
 static void translate_depbits(DisasContext *dc, const uint32_t arg[],
                               const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]],
-                            arg[2], arg[3]);
+    tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]],
+                        arg[2], arg[3]);
+}
+
+static bool test_ill_entry(DisasContext *dc, const uint32_t arg[],
+                           const uint32_t par[])
+{
+    if (arg[0] > 3 || !dc->cwoe) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Illegal entry instruction(pc = %08x)\n", dc->pc);
+        return true;
+    } else {
+        return false;
     }
 }
 
+static uint32_t test_overflow_entry(DisasContext *dc, const uint32_t arg[],
+                                    const uint32_t par[])
+{
+    return 1 << (dc->callinc * 4);
+}
+
 static void translate_entry(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
@@ -1600,60 +1610,41 @@ static void translate_entry(DisasContext *dc, const uint32_t arg[],
     tcg_temp_free(imm);
     tcg_temp_free(s);
     tcg_temp_free(pc);
-    /* This can change tb->flags, so exit tb */
-    gen_jumpi_check_loop_end(dc, -1);
 }
 
 static void translate_extui(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        int maskimm = (1 << arg[3]) - 1;
+    int maskimm = (1 << arg[3]) - 1;
 
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]);
-        tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]);
+    tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm);
+    tcg_temp_free(tmp);
 }
 
-/* par[0]: privileged, par[1]: check memory access */
 static void translate_icache(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if ((!par[0] || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0]) && par[1]) {
 #ifndef CONFIG_USER_ONLY
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_movi_i32(cpu_pc, dc->pc);
-        tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
-        gen_helper_itlb_hit_test(cpu_env, addr);
-        tcg_temp_free(addr);
+    tcg_gen_movi_i32(cpu_pc, dc->pc);
+    tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]);
+    gen_helper_itlb_hit_test(cpu_env, addr);
+    tcg_temp_free(addr);
 #endif
-    }
 }
 
 static void translate_itlb(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check1(dc, arg[0])) {
 #ifndef CONFIG_USER_ONLY
-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);
 
-        gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb);
-        /* This could change memory mapping, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-        tcg_temp_free(dtlb);
+    gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb);
+    tcg_temp_free(dtlb);
 #endif
-    }
-}
-
-static void translate_ill(DisasContext *dc, const uint32_t arg[],
-                          const uint32_t par[])
-{
-    gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
 }
 
 static void translate_j(DisasContext *dc, const uint32_t arg[],
@@ -1665,88 +1656,77 @@ static void translate_j(DisasContext *dc, const uint32_t arg[],
 static void translate_jx(DisasContext *dc, const uint32_t arg[],
                          const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        gen_jump(dc, cpu_R[arg[0]]);
-    }
+    gen_jump(dc, cpu_R[arg[0]]);
 }
 
 static void translate_l32e(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
-        tcg_temp_free(addr);
-    }
+    tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
+    gen_load_store_alignment(dc, 2, addr, false);
+    tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
+    tcg_temp_free(addr);
 }
 
 static void translate_ldst(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        if (par[0] & MO_SIZE) {
-            gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
+    tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
+    if (par[0] & MO_SIZE) {
+        gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
+    }
+    if (par[2]) {
+        if (par[1]) {
+            tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
         }
-        if (par[2]) {
-            if (par[1]) {
-                tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
-            }
-            tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
-        } else {
-            tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
-            if (par[1]) {
-                tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
-            }
+        tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
+    } else {
+        tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]);
+        if (par[1]) {
+            tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
         }
-        tcg_temp_free(addr);
     }
+    tcg_temp_free(addr);
 }
 
 static void translate_l32r(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp;
+    TCGv_i32 tmp;
 
-        if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
-            tmp = tcg_const_i32(dc->raw_arg[1] - 1);
-            tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
-        } else {
-            tmp = tcg_const_i32(arg[1]);
-        }
-        tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
-        tcg_temp_free(tmp);
+    if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
+        tmp = tcg_const_i32(dc->raw_arg[1] - 1);
+        tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
+    } else {
+        tmp = tcg_const_i32(arg[1]);
     }
+    tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring);
+    tcg_temp_free(tmp);
 }
 
 static void translate_loop(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        uint32_t lend = arg[1];
-        TCGv_i32 tmp = tcg_const_i32(lend);
-
-        tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
-        tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
-        gen_helper_wsr_lend(cpu_env, tmp);
-        tcg_temp_free(tmp);
+    uint32_t lend = arg[1];
+    TCGv_i32 tmp = tcg_const_i32(lend);
 
-        if (par[0] != TCG_COND_NEVER) {
-            TCGLabel *label = gen_new_label();
-            tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label);
-            gen_jumpi(dc, lend, 1);
-            gen_set_label(label);
-        }
+    tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
+    tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
+    gen_helper_wsr_lend(cpu_env, tmp);
+    tcg_temp_free(tmp);
 
-        gen_jumpi(dc, dc->base.pc_next, 0);
+    if (par[0] != TCG_COND_NEVER) {
+        TCGLabel *label = gen_new_label();
+        tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label);
+        gen_jumpi(dc, lend, 1);
+        gen_set_label(label);
     }
+
+    gen_jumpi(dc, dc->base.pc_next, 0);
 }
 
 enum {
@@ -1786,78 +1766,60 @@ static void translate_mac16(DisasContext *dc, const uint32_t arg[],
     unsigned half = par[2];
     uint32_t ld_offset = par[3];
     unsigned off = ld_offset ? 2 : 0;
-    uint32_t ar[3] = {0};
-    unsigned n_ar = 0;
-
-    if (op != MAC16_NONE) {
-        if (!is_m1_sr) {
-            ar[n_ar++] = arg[off];
-        }
-        if (!is_m2_sr) {
-            ar[n_ar++] = arg[off + 1];
-        }
-    }
+    TCGv_i32 vaddr = tcg_temp_new_i32();
+    TCGv_i32 mem32 = tcg_temp_new_i32();
 
     if (ld_offset) {
-        ar[n_ar++] = arg[1];
+        tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset);
+        gen_load_store_alignment(dc, 2, vaddr, false);
+        tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
     }
-
-    if (gen_window_check3(dc, ar[0], ar[1], ar[2])) {
-        TCGv_i32 vaddr = tcg_temp_new_i32();
-        TCGv_i32 mem32 = tcg_temp_new_i32();
-
-        if (ld_offset) {
-            tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset);
-            gen_load_store_alignment(dc, 2, vaddr, false);
-            tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
-        }
-        if (op != MAC16_NONE) {
-            TCGv_i32 m1 = gen_mac16_m(is_m1_sr ?
-                                      cpu_SR[MR + arg[off]] :
-                                      cpu_R[arg[off]],
-                                      half & MAC16_HX, op == MAC16_UMUL);
-            TCGv_i32 m2 = gen_mac16_m(is_m2_sr ?
-                                      cpu_SR[MR + arg[off + 1]] :
-                                      cpu_R[arg[off + 1]],
-                                      half & MAC16_XH, op == MAC16_UMUL);
-
-            if (op == MAC16_MUL || op == MAC16_UMUL) {
-                tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
-                if (op == MAC16_UMUL) {
-                    tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
-                } else {
-                    tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
-                }
+    if (op != MAC16_NONE) {
+        TCGv_i32 m1 = gen_mac16_m(is_m1_sr ?
+                                  cpu_SR[MR + arg[off]] :
+                                  cpu_R[arg[off]],
+                                  half & MAC16_HX, op == MAC16_UMUL);
+        TCGv_i32 m2 = gen_mac16_m(is_m2_sr ?
+                                  cpu_SR[MR + arg[off + 1]] :
+                                  cpu_R[arg[off + 1]],
+                                  half & MAC16_XH, op == MAC16_UMUL);
+
+        if (op == MAC16_MUL || op == MAC16_UMUL) {
+            tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
+            if (op == MAC16_UMUL) {
+                tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
             } else {
-                TCGv_i32 lo = tcg_temp_new_i32();
-                TCGv_i32 hi = tcg_temp_new_i32();
-
-                tcg_gen_mul_i32(lo, m1, m2);
-                tcg_gen_sari_i32(hi, lo, 31);
-                if (op == MAC16_MULA) {
-                    tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     lo, hi);
-                } else {
-                    tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     cpu_SR[ACCLO], cpu_SR[ACCHI],
-                                     lo, hi);
-                }
-                tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
-
-                tcg_temp_free_i32(lo);
-                tcg_temp_free_i32(hi);
+                tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
             }
-            tcg_temp_free(m1);
-            tcg_temp_free(m2);
-        }
-        if (ld_offset) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], vaddr);
-            tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32);
+        } else {
+            TCGv_i32 lo = tcg_temp_new_i32();
+            TCGv_i32 hi = tcg_temp_new_i32();
+
+            tcg_gen_mul_i32(lo, m1, m2);
+            tcg_gen_sari_i32(hi, lo, 31);
+            if (op == MAC16_MULA) {
+                tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 lo, hi);
+            } else {
+                tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 cpu_SR[ACCLO], cpu_SR[ACCHI],
+                                 lo, hi);
+            }
+            tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
+
+            tcg_temp_free_i32(lo);
+            tcg_temp_free_i32(hi);
         }
-        tcg_temp_free(vaddr);
-        tcg_temp_free(mem32);
+        tcg_temp_free(m1);
+        tcg_temp_free(m2);
     }
+    if (ld_offset) {
+        tcg_gen_mov_i32(cpu_R[arg[1]], vaddr);
+        tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32);
+    }
+    tcg_temp_free(vaddr);
+    tcg_temp_free(mem32);
 }
 
 static void translate_memw(DisasContext *dc, const uint32_t arg[],
@@ -1869,139 +1831,110 @@ static void translate_memw(DisasContext *dc, const uint32_t arg[],
 static void translate_smin(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_umin(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_smax(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_umax(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_mov(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
 }
 
 static void translate_movcond(DisasContext *dc, const uint32_t arg[],
                               const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 zero = tcg_const_i32(0);
 
-        tcg_gen_movcond_i32(par[0], cpu_R[arg[0]],
-                            cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_movcond_i32(par[0], cpu_R[arg[0]],
+                        cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]);
+    tcg_temp_free(zero);
 }
 
 static void translate_movi(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]);
-    }
+    tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]);
 }
 
 static void translate_movp(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 tmp = tcg_temp_new_i32();
 
-        tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
-        tcg_gen_movcond_i32(par[0],
-                            cpu_R[arg[0]], tmp, zero,
-                            cpu_R[arg[1]], cpu_R[arg[0]]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
+    tcg_gen_movcond_i32(par[0],
+                        cpu_R[arg[0]], tmp, zero,
+                        cpu_R[arg[1]], cpu_R[arg[0]]);
+    tcg_temp_free(tmp);
+    tcg_temp_free(zero);
 }
 
 static void translate_movsp(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 pc = tcg_const_i32(dc->pc);
-        gen_helper_movsp(cpu_env, pc);
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        tcg_temp_free(pc);
-    }
+    tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
 }
 
 static void translate_mul16(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 v1 = tcg_temp_new_i32();
-        TCGv_i32 v2 = tcg_temp_new_i32();
+    TCGv_i32 v1 = tcg_temp_new_i32();
+    TCGv_i32 v2 = tcg_temp_new_i32();
 
-        if (par[0]) {
-            tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]);
-            tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]);
-        } else {
-            tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]);
-            tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]);
-        }
-        tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2);
-        tcg_temp_free(v2);
-        tcg_temp_free(v1);
+    if (par[0]) {
+        tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]);
+        tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]);
+    } else {
+        tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]);
+        tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]);
     }
+    tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2);
+    tcg_temp_free(v2);
+    tcg_temp_free(v1);
 }
 
 static void translate_mull(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_mulh(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 lo = tcg_temp_new();
+    TCGv_i32 lo = tcg_temp_new();
 
-        if (par[0]) {
-            tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-        tcg_temp_free(lo);
+    if (par[0]) {
+        tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
+    } else {
+        tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
     }
+    tcg_temp_free(lo);
 }
 
 static void translate_neg(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
 }
 
 static void translate_nop(DisasContext *dc, const uint32_t arg[],
@@ -2012,110 +1945,82 @@ static void translate_nop(DisasContext *dc, const uint32_t arg[],
 static void translate_nsa(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
 }
 
 static void translate_nsau(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32);
-    }
+    tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32);
 }
 
 static void translate_or(DisasContext *dc, const uint32_t arg[],
                          const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_ptlb(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
 #ifndef CONFIG_USER_ONLY
-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);
 
-        tcg_gen_movi_i32(cpu_pc, dc->pc);
-        gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
-        tcg_temp_free(dtlb);
+    tcg_gen_movi_i32(cpu_pc, dc->pc);
+    gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
+    tcg_temp_free(dtlb);
 #endif
-    }
-}
-
-static void gen_zero_check(DisasContext *dc, const uint32_t arg[])
-{
-    TCGLabel *label = gen_new_label();
-
-    tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label);
-    gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
-    gen_set_label(label);
 }
 
 static void translate_quos(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGLabel *label1 = gen_new_label();
-        TCGLabel *label2 = gen_new_label();
-
-        gen_zero_check(dc, arg);
-
-        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000,
-                            label1);
-        tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff,
-                            label1);
-        tcg_gen_movi_i32(cpu_R[arg[0]],
-                         par[0] ? 0x80000000 : 0);
-        tcg_gen_br(label2);
-        gen_set_label(label1);
-        if (par[0]) {
-            tcg_gen_div_i32(cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_rem_i32(cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-        gen_set_label(label2);
+    TCGLabel *label1 = gen_new_label();
+    TCGLabel *label2 = gen_new_label();
+
+    tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000,
+                        label1);
+    tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff,
+                        label1);
+    tcg_gen_movi_i32(cpu_R[arg[0]],
+                     par[0] ? 0x80000000 : 0);
+    tcg_gen_br(label2);
+    gen_set_label(label1);
+    if (par[0]) {
+        tcg_gen_div_i32(cpu_R[arg[0]],
+                        cpu_R[arg[1]], cpu_R[arg[2]]);
+    } else {
+        tcg_gen_rem_i32(cpu_R[arg[0]],
+                        cpu_R[arg[1]], cpu_R[arg[2]]);
     }
+    gen_set_label(label2);
 }
 
 static void translate_quou(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        gen_zero_check(dc, arg);
-        if (par[0]) {
-            tcg_gen_divu_i32(cpu_R[arg[0]],
-                             cpu_R[arg[1]], cpu_R[arg[2]]);
-        } else {
-            tcg_gen_remu_i32(cpu_R[arg[0]],
-                             cpu_R[arg[1]], cpu_R[arg[2]]);
-        }
-    }
+    tcg_gen_divu_i32(cpu_R[arg[0]],
+                     cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_read_impwire(DisasContext *dc, const uint32_t arg[],
                                    const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        /* TODO: GPIO32 may be a part of coprocessor */
-        tcg_gen_movi_i32(cpu_R[arg[0]], 0);
-    }
+    /* TODO: GPIO32 may be a part of coprocessor */
+    tcg_gen_movi_i32(cpu_R[arg[0]], 0);
+}
+
+static void translate_remu(DisasContext *dc, const uint32_t arg[],
+                           const uint32_t par[])
+{
+    tcg_gen_remu_i32(cpu_R[arg[0]],
+                     cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_rer(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]);
-    }
+    gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]);
 }
 
 static void translate_ret(DisasContext *dc, const uint32_t arg[],
@@ -2124,6 +2029,22 @@ static void translate_ret(DisasContext *dc, const uint32_t arg[],
     gen_jump(dc, cpu_R[0]);
 }
 
+static bool test_ill_retw(DisasContext *dc, const uint32_t arg[],
+                          const uint32_t par[])
+{
+    if (!dc->cwoe) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "Illegal retw instruction(pc = %08x)\n", dc->pc);
+        return true;
+    } else {
+        TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+        gen_helper_test_ill_retw(cpu_env, tmp);
+        tcg_temp_free(tmp);
+        return false;
+    }
+}
+
 static void translate_retw(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
@@ -2136,122 +2057,95 @@ static void translate_retw(DisasContext *dc, const uint32_t arg[],
 static void translate_rfde(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
-        gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
-    }
+    gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
 }
 
 static void translate_rfe(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1]);
-    }
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
+    gen_jump(dc, cpu_SR[EPC1]);
 }
 
 static void translate_rfi(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
-        tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]);
-    }
+    tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]);
+    gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]);
 }
 
 static void translate_rfw(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
-        TCGv_i32 tmp = tcg_const_i32(1);
-
-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
-        tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
-
-        if (par[0]) {
-            tcg_gen_andc_i32(cpu_SR[WINDOW_START],
-                             cpu_SR[WINDOW_START], tmp);
-        } else {
-            tcg_gen_or_i32(cpu_SR[WINDOW_START],
-                           cpu_SR[WINDOW_START], tmp);
-        }
+    TCGv_i32 tmp = tcg_const_i32(1);
 
-        gen_helper_restore_owb(cpu_env);
-        gen_check_interrupts(dc);
-        gen_jump(dc, cpu_SR[EPC1]);
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
+    tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
 
-        tcg_temp_free(tmp);
+    if (par[0]) {
+        tcg_gen_andc_i32(cpu_SR[WINDOW_START],
+                         cpu_SR[WINDOW_START], tmp);
+    } else {
+        tcg_gen_or_i32(cpu_SR[WINDOW_START],
+                       cpu_SR[WINDOW_START], tmp);
     }
+
+    tcg_temp_free(tmp);
+    gen_helper_restore_owb(cpu_env);
+    gen_jump(dc, cpu_SR[EPC1]);
 }
 
 static void translate_rotw(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
-        TCGv_i32 tmp = tcg_const_i32(arg[0]);
-        gen_helper_rotw(cpu_env, tmp);
-        tcg_temp_free(tmp);
-        /* This can change tb->flags, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-    }
+    TCGv_i32 tmp = tcg_const_i32(arg[0]);
+    gen_helper_rotw(cpu_env, tmp);
+    tcg_temp_free(tmp);
 }
 
 static void translate_rsil(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check1(dc, arg[0])) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]);
-        tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
-        tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]);
-        gen_check_interrupts(dc);
-        gen_jumpi_check_loop_end(dc, 0);
-    }
+    tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]);
+    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
+    tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]);
+}
+
+static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[],
+                         const uint32_t par[])
+{
+    return !check_sr(dc, par[0], SR_R);
 }
 
 static void translate_rsr(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_sr(dc, par[0], SR_R) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        if (gen_rsr(dc, cpu_R[arg[0]], par[0])) {
-            gen_jumpi_check_loop_end(dc, 0);
-        }
-    }
+    gen_rsr(dc, cpu_R[arg[0]], par[0]);
 }
 
 static void translate_rtlb(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
+#ifndef CONFIG_USER_ONLY
     static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
                                    TCGv_i32 a2) = {
-#ifndef CONFIG_USER_ONLY
         gen_helper_rtlb0,
         gen_helper_rtlb1,
-#endif
     };
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);
 
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
-
-        helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
-        tcg_temp_free(dtlb);
-    }
+    helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb);
+    tcg_temp_free(dtlb);
+#endif
 }
 
 static void translate_rur(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        if (uregnames[par[0]].name) {
-            tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
-        } else {
-            qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
-        }
+    if (uregnames[par[0]].name) {
+        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
+    } else {
+        qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
     }
 }
 
@@ -2279,78 +2173,75 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
 static void translate_s32c1i(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 tmp = tcg_temp_local_new_i32();
-        TCGv_i32 addr = tcg_temp_local_new_i32();
-
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, true);
-        gen_check_atomctl(dc, addr);
-        tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1],
-                                   tmp, dc->cring, MO_TEUL);
-        tcg_temp_free(addr);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_local_new_i32();
+    TCGv_i32 addr = tcg_temp_local_new_i32();
+
+    tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
+    tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
+    gen_load_store_alignment(dc, 2, addr, true);
+    gen_check_atomctl(dc, addr);
+    tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1],
+                               tmp, dc->cring, MO_TEUL);
+    tcg_temp_free(addr);
+    tcg_temp_free(tmp);
 }
 
 static void translate_s32e(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
-        tcg_temp_free(addr);
-    }
+    tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
+    gen_load_store_alignment(dc, 2, addr, false);
+    tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL);
+    tcg_temp_free(addr);
 }
 
 static void translate_salt(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_setcond_i32(par[0],
-                            cpu_R[arg[0]],
-                            cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_setcond_i32(par[0],
+                        cpu_R[arg[0]],
+                        cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_sext(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        int shift = 31 - arg[2];
+    int shift = 31 - arg[2];
 
-        if (shift == 24) {
-            tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        } else if (shift == 16) {
-            tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
-        } else {
-            TCGv_i32 tmp = tcg_temp_new_i32();
-            tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift);
-            tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift);
-            tcg_temp_free(tmp);
-        }
+    if (shift == 24) {
+        tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
+    } else if (shift == 16) {
+        tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]);
+    } else {
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift);
+        tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift);
+        tcg_temp_free(tmp);
+    }
+}
+
+static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[],
+                             const uint32_t par[])
+{
+#ifdef CONFIG_USER_ONLY
+    bool ill = true;
+#else
+    bool ill = !semihosting_enabled();
+#endif
+    if (ill) {
+        qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
     }
+    return ill;
 }
 
 static void translate_simcall(DisasContext *dc, const uint32_t arg[],
                               const uint32_t par[])
 {
 #ifndef CONFIG_USER_ONLY
-    if (semihosting_enabled()) {
-        if (gen_check_privilege(dc)) {
-            gen_helper_simcall(cpu_env);
-        }
-    } else
+    gen_helper_simcall(cpu_env);
 #endif
-    {
-        qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
-        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
-    }
 }
 
 /*
@@ -2371,76 +2262,64 @@ static void translate_simcall(DisasContext *dc, const uint32_t arg[],
 static void translate_sll(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            TCGv_i32 s = tcg_const_i32(32);
-            tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
-            tcg_gen_andi_i32(s, s, 0x3f);
-            tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift_reg(shl, s);
-            tcg_temp_free(s);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        TCGv_i32 s = tcg_const_i32(32);
+        tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
+        tcg_gen_andi_i32(s, s, 0x3f);
+        tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
+        gen_shift_reg(shl, s);
+        tcg_temp_free(s);
     }
 }
 
 static void translate_slli(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (arg[2] == 32) {
-            qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
-                          arg[0], arg[1]);
-        }
-        tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
+    if (arg[2] == 32) {
+        qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
+                      arg[0], arg[1]);
     }
+    tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
 }
 
 static void translate_sra(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift(sar);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]);
+        gen_shift(sar);
     }
 }
 
 static void translate_srai(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
 }
 
 static void translate_src(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i64 v = tcg_temp_new_i64();
-        tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]);
-        gen_shift(shr);
-    }
+    TCGv_i64 v = tcg_temp_new_i64();
+    tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]);
+    gen_shift(shr);
 }
 
 static void translate_srl(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        if (dc->sar_m32_5bit) {
-            tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
-        } else {
-            TCGv_i64 v = tcg_temp_new_i64();
-            tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
-            gen_shift(shr);
-        }
+    if (dc->sar_m32_5bit) {
+        tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]);
+    } else {
+        TCGv_i64 v = tcg_temp_new_i64();
+        tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]);
+        gen_shift(shr);
     }
 }
 
@@ -2450,31 +2329,25 @@ static void translate_srl(DisasContext *dc, const uint32_t arg[],
 static void translate_srli(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
-    }
+    tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]);
 }
 
 static void translate_ssa8b(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
-        gen_left_shift_sar(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
+    gen_left_shift_sar(dc, tmp);
+    tcg_temp_free(tmp);
 }
 
 static void translate_ssa8l(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
-        gen_right_shift_sar(dc, tmp);
-        tcg_temp_free(tmp);
-    }
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3);
+    gen_right_shift_sar(dc, tmp);
+    tcg_temp_free(tmp);
 }
 
 static void translate_ssai(DisasContext *dc, const uint32_t arg[],
@@ -2488,168 +2361,147 @@ static void translate_ssai(DisasContext *dc, const uint32_t arg[],
 static void translate_ssl(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        gen_left_shift_sar(dc, cpu_R[arg[0]]);
-    }
+    gen_left_shift_sar(dc, cpu_R[arg[0]]);
 }
 
 static void translate_ssr(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        gen_right_shift_sar(dc, cpu_R[arg[0]]);
-    }
+    gen_right_shift_sar(dc, cpu_R[arg[0]]);
 }
 
 static void translate_sub(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
 }
 
 static void translate_subx(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
-        tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
-        tcg_temp_free(tmp);
-    }
-}
-
-static void translate_syscall(DisasContext *dc, const uint32_t arg[],
-                              const uint32_t par[])
-{
-    gen_exception_cause(dc, SYSCALL_CAUSE);
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]);
+    tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]);
+    tcg_temp_free(tmp);
 }
 
 static void translate_waiti(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_privilege(dc)) {
 #ifndef CONFIG_USER_ONLY
-        gen_waiti(dc, arg[0]);
+    gen_waiti(dc, arg[0]);
 #endif
-    }
 }
 
 static void translate_wtlb(DisasContext *dc, const uint32_t arg[],
                            const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
 #ifndef CONFIG_USER_ONLY
-        TCGv_i32 dtlb = tcg_const_i32(par[0]);
+    TCGv_i32 dtlb = tcg_const_i32(par[0]);
 
-        gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb);
-        /* This could change memory mapping, so exit tb */
-        gen_jumpi_check_loop_end(dc, -1);
-        tcg_temp_free(dtlb);
+    gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb);
+    tcg_temp_free(dtlb);
 #endif
-    }
 }
 
 static void translate_wer(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_privilege(dc) &&
-        gen_window_check2(dc, arg[0], arg[1])) {
-        gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]);
 }
 
 static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[],
                                      const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[0], arg[1])) {
-        /* TODO: GPIO32 may be a part of coprocessor */
-        tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]);
-    }
+    /* TODO: GPIO32 may be a part of coprocessor */
+    tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]);
+}
+
+static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[],
+                         const uint32_t par[])
+{
+    return !check_sr(dc, par[0], SR_W);
 }
 
 static void translate_wsr(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_sr(dc, par[0], SR_W) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        gen_wsr(dc, par[0], cpu_R[arg[0]]);
-    }
+    gen_wsr(dc, par[0], cpu_R[arg[0]]);
 }
 
 static void translate_wur(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0])) {
-        if (uregnames[par[0]].name) {
-            gen_wur(par[0], cpu_R[arg[0]]);
-        } else {
-            qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
-        }
+    if (uregnames[par[0]].name) {
+        gen_wur(par[0], cpu_R[arg[0]]);
+    } else {
+        qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
     }
 }
 
 static void translate_xor(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_window_check3(dc, arg[0], arg[1], arg[2])) {
-        tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
-    }
+    tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]);
+}
+
+static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[],
+                         const uint32_t par[])
+{
+    return !check_sr(dc, par[0], SR_X);
 }
 
 static void translate_xsr(DisasContext *dc, const uint32_t arg[],
                           const uint32_t par[])
 {
-    if (gen_check_sr(dc, par[0], SR_X) &&
-        (par[0] < 64 || gen_check_privilege(dc)) &&
-        gen_window_check1(dc, arg[0])) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        bool rsr_end, wsr_end;
+    TCGv_i32 tmp = tcg_temp_new_i32();
 
-        tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
-        rsr_end = gen_rsr(dc, cpu_R[arg[0]], par[0]);
-        wsr_end = gen_wsr(dc, par[0], tmp);
-        tcg_temp_free(tmp);
-        if (rsr_end && !wsr_end) {
-            gen_jumpi_check_loop_end(dc, 0);
-        }
-    }
+    tcg_gen_mov_i32(tmp, cpu_R[arg[0]]);
+    gen_rsr(dc, cpu_R[arg[0]], par[0]);
+    gen_wsr(dc, par[0], tmp);
+    tcg_temp_free(tmp);
 }
 
 static const XtensaOpcodeOps core_ops[] = {
     {
         .name = "abs",
         .translate = translate_abs,
+        .windowed_register_op = 0x3,
     }, {
         .name = "add",
         .translate = translate_add,
+        .windowed_register_op = 0x7,
     }, {
         .name = "add.n",
         .translate = translate_add,
+        .windowed_register_op = 0x7,
     }, {
         .name = "addi",
         .translate = translate_addi,
+        .windowed_register_op = 0x3,
     }, {
         .name = "addi.n",
         .translate = translate_addi,
+        .windowed_register_op = 0x3,
     }, {
         .name = "addmi",
         .translate = translate_addi,
+        .windowed_register_op = 0x3,
     }, {
         .name = "addx2",
         .translate = translate_addx,
         .par = (const uint32_t[]){1},
+        .windowed_register_op = 0x7,
     }, {
         .name = "addx4",
         .translate = translate_addx,
         .par = (const uint32_t[]){2},
+        .windowed_register_op = 0x7,
     }, {
         .name = "addx8",
         .translate = translate_addx,
         .par = (const uint32_t[]){3},
+        .windowed_register_op = 0x7,
     }, {
         .name = "all4",
         .translate = translate_all,
@@ -2661,6 +2513,7 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "and",
         .translate = translate_and,
+        .windowed_register_op = 0x7,
     }, {
         .name = "andb",
         .translate = translate_boolean,
@@ -2681,42 +2534,52 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "ball",
         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bany",
         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bbc",
         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bbci",
         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bbs",
         .translate = translate_bb,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bbsi",
         .translate = translate_bbi,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "beq",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x3,
     }, {
         .name = "beqi",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x1,
     }, {
         .name = "beqz",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x1,
     }, {
         .name = "beqz.n",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bf",
         .translate = translate_bp,
@@ -2725,74 +2588,92 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "bge",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bgei",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bgeu",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_GEU},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bgeui",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_GEU},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bgez",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_GE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "blt",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x3,
     }, {
         .name = "blti",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bltu",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_LTU},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bltui",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_LTU},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bltz",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bnall",
         .translate = translate_ball,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bne",
         .translate = translate_b,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "bnei",
         .translate = translate_bi,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bnez",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bnez.n",
         .translate = translate_bz,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "bnone",
         .translate = translate_bany,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x3,
     }, {
         .name = "break",
-        .translate = translate_break,
+        .translate = translate_nop,
         .par = (const uint32_t[]){DEBUGCAUSE_BI},
+        .op_flags = XTENSA_OP_DEBUG_BREAK,
     }, {
         .name = "break.n",
-        .translate = translate_break,
+        .translate = translate_nop,
         .par = (const uint32_t[]){DEBUGCAUSE_BN},
+        .op_flags = XTENSA_OP_DEBUG_BREAK,
     }, {
         .name = "bt",
         .translate = translate_bp,
@@ -2803,100 +2684,123 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "call12",
         .translate = translate_callw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){3},
     }, {
         .name = "call4",
         .translate = translate_callw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){1},
     }, {
         .name = "call8",
         .translate = translate_callw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){2},
     }, {
         .name = "callx0",
         .translate = translate_callx0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "callx12",
         .translate = translate_callxw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){3},
+        .windowed_register_op = 0x1,
     }, {
         .name = "callx4",
         .translate = translate_callxw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "callx8",
         .translate = translate_callxw,
+        .test_overflow = test_overflow_callw,
         .par = (const uint32_t[]){2},
+        .windowed_register_op = 0x1,
     }, {
         .name = "clamps",
         .translate = translate_clamps,
+        .windowed_register_op = 0x3,
     }, {
         .name = "clrb_expstate",
         .translate = translate_clrb_expstate,
     }, {
         .name = "const16",
         .translate = translate_const16,
+        .windowed_register_op = 0x1,
     }, {
         .name = "depbits",
         .translate = translate_depbits,
+        .windowed_register_op = 0x3,
     }, {
         .name = "dhi",
         .translate = translate_dcache,
-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dhu",
         .translate = translate_dcache,
-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dhwb",
         .translate = translate_dcache,
-        .par = (const uint32_t[]){false, true},
+        .windowed_register_op = 0x1,
     }, {
         .name = "dhwbi",
         .translate = translate_dcache,
-        .par = (const uint32_t[]){false, true},
+        .windowed_register_op = 0x1,
     }, {
         .name = "dii",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "diu",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "diwb",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "diwbi",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dpfl",
         .translate = translate_dcache,
-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dpfr",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dpfro",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dpfw",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dpfwo",
-        .translate = translate_dcache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,
+        .windowed_register_op = 0x1,
     }, {
         .name = "dsync",
         .translate = translate_nop,
     }, {
         .name = "entry",
         .translate = translate_entry,
+        .test_ill = test_ill_entry,
+        .test_overflow = test_overflow_entry,
+        .op_flags = XTENSA_OP_EXIT_TB_M1,
     }, {
         .name = "esync",
         .translate = translate_nop,
@@ -2906,53 +2810,62 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "extui",
         .translate = translate_extui,
+        .windowed_register_op = 0x3,
     }, {
         .name = "extw",
         .translate = translate_memw,
     }, {
         .name = "hwwdtlba",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "hwwitlba",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "idtlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ihi",
         .translate = translate_icache,
-        .par = (const uint32_t[]){false, true},
+        .windowed_register_op = 0x1,
     }, {
         .name = "ihu",
         .translate = translate_icache,
-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "iii",
-        .translate = translate_icache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "iitlb",
         .translate = translate_itlb,
         .par = (const uint32_t[]){false},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "iiu",
-        .translate = translate_icache,
-        .par = (const uint32_t[]){true, false},
+        .translate = translate_nop,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ill",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "ill.n",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "ipf",
-        .translate = translate_icache,
-        .par = (const uint32_t[]){false, false},
+        .translate = translate_nop,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ipfl",
         .translate = translate_icache,
-        .par = (const uint32_t[]){true, true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "isync",
         .translate = translate_nop,
@@ -2962,161 +2875,204 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "jx",
         .translate = translate_jx,
+        .windowed_register_op = 0x1,
     }, {
         .name = "l16si",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TESW, false, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "l16ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "l32ai",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "l32e",
         .translate = translate_l32e,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "l32i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "l32i.n",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "l32r",
         .translate = translate_l32r,
+        .windowed_register_op = 0x1,
     }, {
         .name = "l8ui",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, false},
+        .windowed_register_op = 0x3,
     }, {
         .name = "lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "ldpte",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "loop",
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NEVER},
+        .windowed_register_op = 0x1,
     }, {
         .name = "loopgtz",
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_GT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "loopnez",
         .translate = translate_loop,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "max",
         .translate = translate_smax,
+        .windowed_register_op = 0x7,
     }, {
         .name = "maxu",
         .translate = translate_umax,
+        .windowed_register_op = 0x7,
     }, {
         .name = "memw",
         .translate = translate_memw,
     }, {
         .name = "min",
         .translate = translate_smin,
+        .windowed_register_op = 0x7,
     }, {
         .name = "minu",
         .translate = translate_umin,
+        .windowed_register_op = 0x7,
     }, {
         .name = "mov",
         .translate = translate_mov,
+        .windowed_register_op = 0x3,
     }, {
         .name = "mov.n",
         .translate = translate_mov,
+        .windowed_register_op = 0x3,
     }, {
         .name = "moveqz",
         .translate = translate_movcond,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x7,
     }, {
         .name = "movf",
         .translate = translate_movp,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x3,
     }, {
         .name = "movgez",
         .translate = translate_movcond,
         .par = (const uint32_t[]){TCG_COND_GE},
+        .windowed_register_op = 0x7,
     }, {
         .name = "movi",
         .translate = translate_movi,
+        .windowed_register_op = 0x1,
     }, {
         .name = "movi.n",
         .translate = translate_movi,
+        .windowed_register_op = 0x1,
     }, {
         .name = "movltz",
         .translate = translate_movcond,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x7,
     }, {
         .name = "movnez",
         .translate = translate_movcond,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x7,
     }, {
         .name = "movsp",
         .translate = translate_movsp,
+        .windowed_register_op = 0x3,
+        .op_flags = XTENSA_OP_ALLOCA,
     }, {
         .name = "movt",
         .translate = translate_movp,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mul.aa.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mul.aa.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mul.aa.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mul.aa.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mul.ad.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mul.ad.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mul.ad.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mul.ad.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mul.da.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mul.da.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mul.da.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mul.da.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mul.dd.hh",
         .translate = translate_mac16,
@@ -3137,90 +3093,112 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mul16s",
         .translate = translate_mul16,
         .par = (const uint32_t[]){true},
+        .windowed_register_op = 0x7,
     }, {
         .name = "mul16u",
         .translate = translate_mul16,
         .par = (const uint32_t[]){false},
+        .windowed_register_op = 0x7,
     }, {
         .name = "mula.aa.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mula.aa.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mula.aa.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mula.aa.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "mula.ad.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mula.ad.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mula.ad.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mula.ad.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "mula.da.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.da.hh.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.hh.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.da.hl.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.hl.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.da.lh.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.lh.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.da.ll.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.da.ll.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4},
+        .windowed_register_op = 0xa,
     }, {
         .name = "mula.dd.hh",
         .translate = translate_mac16,
@@ -3229,10 +3207,12 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mula.dd.hh.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.hh.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.hl",
         .translate = translate_mac16,
@@ -3241,10 +3221,12 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mula.dd.hl.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.hl.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.lh",
         .translate = translate_mac16,
@@ -3253,10 +3235,12 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mula.dd.lh.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.lh.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.ll",
         .translate = translate_mac16,
@@ -3265,61 +3249,76 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mula.dd.ll.lddec",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mula.dd.ll.ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4},
+        .windowed_register_op = 0x2,
     }, {
         .name = "mull",
         .translate = translate_mull,
+        .windowed_register_op = 0x7,
     }, {
         .name = "muls.aa.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "muls.aa.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "muls.aa.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "muls.aa.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "muls.ad.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "muls.ad.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "muls.ad.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "muls.ad.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0},
+        .windowed_register_op = 0x1,
     }, {
         .name = "muls.da.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "muls.da.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "muls.da.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "muls.da.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0},
+        .windowed_register_op = 0x2,
     }, {
         .name = "muls.dd.hh",
         .translate = translate_mac16,
@@ -3340,13 +3339,16 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "mulsh",
         .translate = translate_mulh,
         .par = (const uint32_t[]){true},
+        .windowed_register_op = 0x7,
     }, {
         .name = "muluh",
         .translate = translate_mulh,
         .par = (const uint32_t[]){false},
+        .windowed_register_op = 0x7,
     }, {
         .name = "neg",
         .translate = translate_neg,
+        .windowed_register_op = 0x3,
     }, {
         .name = "nop",
         .translate = translate_nop,
@@ -3356,12 +3358,15 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "nsa",
         .translate = translate_nsa,
+        .windowed_register_op = 0x3,
     }, {
         .name = "nsau",
         .translate = translate_nsau,
+        .windowed_register_op = 0x3,
     }, {
         .name = "or",
         .translate = translate_or,
+        .windowed_register_op = 0x7,
     }, {
         .name = "orb",
         .translate = translate_boolean,
@@ -3374,40 +3379,57 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "pdtlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "pitlb",
         .translate = translate_ptlb,
         .par = (const uint32_t[]){false},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "quos",
         .translate = translate_quos,
         .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
+        .windowed_register_op = 0x7,
     }, {
         .name = "quou",
         .translate = translate_quou,
-        .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
+        .windowed_register_op = 0x7,
     }, {
         .name = "rdtlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 0},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "rdtlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){true, 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "read_impwire",
         .translate = translate_read_impwire,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rems",
         .translate = translate_quos,
         .par = (const uint32_t[]){false},
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
+        .windowed_register_op = 0x7,
     }, {
         .name = "remu",
-        .translate = translate_quou,
-        .par = (const uint32_t[]){false},
+        .translate = translate_remu,
+        .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
+        .windowed_register_op = 0x7,
     }, {
         .name = "rer",
         .translate = translate_rer,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "ret",
         .translate = translate_ret,
@@ -3417,350 +3439,584 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "retw",
         .translate = translate_retw,
+        .test_ill = test_ill_retw,
+        .op_flags = XTENSA_OP_UNDERFLOW,
     }, {
         .name = "retw.n",
         .translate = translate_retw,
+        .test_ill = test_ill_retw,
+        .op_flags = XTENSA_OP_UNDERFLOW,
     }, {
         .name = "rfdd",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "rfde",
         .translate = translate_rfde,
+        .op_flags = XTENSA_OP_PRIVILEGED,
     }, {
         .name = "rfdo",
-        .translate = translate_ill,
+        .op_flags = XTENSA_OP_ILL,
     }, {
         .name = "rfe",
         .translate = translate_rfe,
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
     }, {
         .name = "rfi",
         .translate = translate_rfi,
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
     }, {
         .name = "rfwo",
         .translate = translate_rfw,
         .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
     }, {
         .name = "rfwu",
         .translate = translate_rfw,
         .par = (const uint32_t[]){false},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
     }, {
         .name = "ritlb0",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 0},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "ritlb1",
         .translate = translate_rtlb,
         .par = (const uint32_t[]){false, 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "rotw",
         .translate = translate_rotw,
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
     }, {
         .name = "rsil",
         .translate = translate_rsil,
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.176",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){176},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.208",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){208},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.acchi",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ACCHI},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.acclo",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ACCLO},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.atomctl",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ATOMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.br",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){BR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.cacheattr",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CACHEATTR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ccompare0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CCOMPARE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ccompare1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CCOMPARE + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ccompare2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CCOMPARE + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ccount",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CCOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.configid0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CONFIGID0},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.configid1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CONFIGID1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.cpenable",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){CPENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.dbreaka0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.dbreaka1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.dbreakc0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DBREAKC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.dbreakc1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ddr",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.debugcause",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DEBUGCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.depc",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DEPC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.dtlbcfg",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){DTLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc3",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc4",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc5",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc6",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.epc7",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPC1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps3",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps4",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps5",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps6",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.eps7",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EPS2 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.exccause",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave3",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave4",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave5",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave6",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excsave7",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.excvaddr",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){EXCVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ibreaka0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){IBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ibreaka1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){IBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ibreakenable",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){IBREAKENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.icount",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ICOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.icountlevel",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ICOUNTLEVEL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.intclear",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){INTCLEAR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.intenable",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){INTENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.interrupt",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.intset",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.itlbcfg",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){ITLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.lbeg",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){LBEG},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.lcount",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){LCOUNT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.lend",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){LEND},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.litbase",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){LITBASE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.m0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.m1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MR + 1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.m2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MR + 2},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.m3",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MR + 3},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.memctl",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MEMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.misc0",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MISC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.misc1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MISC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.misc2",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MISC + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.misc3",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){MISC + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.prid",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){PRID},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ps",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){PS},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.ptevaddr",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){PTEVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.rasid",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){RASID},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.sar",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){SAR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.scompare1",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){SCOMPARE1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.vecbase",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){VECBASE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.windowbase",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){WINDOW_BASE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsr.windowstart",
         .translate = translate_rsr,
+        .test_ill = test_ill_rsr,
         .par = (const uint32_t[]){WINDOW_START},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "rsync",
         .translate = translate_nop,
@@ -3768,479 +4024,769 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "rur.expstate",
         .translate = translate_rur,
         .par = (const uint32_t[]){EXPSTATE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "rur.fcr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FCR},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "rur.fsr",
         .translate = translate_rur,
         .par = (const uint32_t[]){FSR},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "rur.threadptr",
         .translate = translate_rur,
         .par = (const uint32_t[]){THREADPTR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "s16i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUW, false, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32c1i",
         .translate = translate_s32c1i,
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32e",
         .translate = translate_s32e,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32i.n",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32nb",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, false, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "s32ri",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_TEUL, true, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "s8i",
         .translate = translate_ldst,
         .par = (const uint32_t[]){MO_UB, false, true},
+        .windowed_register_op = 0x3,
     }, {
         .name = "salt",
         .translate = translate_salt,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x7,
     }, {
         .name = "saltu",
         .translate = translate_salt,
         .par = (const uint32_t[]){TCG_COND_LTU},
+        .windowed_register_op = 0x7,
     }, {
         .name = "setb_expstate",
         .translate = translate_setb_expstate,
     }, {
         .name = "sext",
         .translate = translate_sext,
+        .windowed_register_op = 0x3,
     }, {
         .name = "simcall",
         .translate = translate_simcall,
+        .test_ill = test_ill_simcall,
+        .op_flags = XTENSA_OP_PRIVILEGED,
     }, {
         .name = "sll",
         .translate = translate_sll,
+        .windowed_register_op = 0x3,
     }, {
         .name = "slli",
         .translate = translate_slli,
+        .windowed_register_op = 0x3,
     }, {
         .name = "sra",
         .translate = translate_sra,
+        .windowed_register_op = 0x3,
     }, {
         .name = "srai",
         .translate = translate_srai,
+        .windowed_register_op = 0x3,
     }, {
         .name = "src",
         .translate = translate_src,
+        .windowed_register_op = 0x7,
     }, {
         .name = "srl",
         .translate = translate_srl,
+        .windowed_register_op = 0x3,
     }, {
         .name = "srli",
         .translate = translate_srli,
+        .windowed_register_op = 0x3,
     }, {
         .name = "ssa8b",
         .translate = translate_ssa8b,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ssa8l",
         .translate = translate_ssa8l,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ssai",
         .translate = translate_ssai,
     }, {
         .name = "ssl",
         .translate = translate_ssl,
+        .windowed_register_op = 0x1,
     }, {
         .name = "ssr",
         .translate = translate_ssr,
+        .windowed_register_op = 0x1,
     }, {
         .name = "sub",
         .translate = translate_sub,
+        .windowed_register_op = 0x7,
     }, {
         .name = "subx2",
         .translate = translate_subx,
         .par = (const uint32_t[]){1},
+        .windowed_register_op = 0x7,
     }, {
         .name = "subx4",
         .translate = translate_subx,
         .par = (const uint32_t[]){2},
+        .windowed_register_op = 0x7,
     }, {
         .name = "subx8",
         .translate = translate_subx,
         .par = (const uint32_t[]){3},
+        .windowed_register_op = 0x7,
     }, {
         .name = "syscall",
-        .translate = translate_syscall,
+        .op_flags = XTENSA_OP_SYSCALL,
     }, {
         .name = "umul.aa.hh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "umul.aa.hl",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "umul.aa.lh",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "umul.aa.ll",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0},
+        .windowed_register_op = 0x3,
     }, {
         .name = "waiti",
         .translate = translate_waiti,
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
     }, {
         .name = "wdtlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){true},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x3,
     }, {
         .name = "wer",
         .translate = translate_wer,
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x3,
     }, {
         .name = "witlb",
         .translate = translate_wtlb,
         .par = (const uint32_t[]){false},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x3,
     }, {
         .name = "wrmsk_expstate",
         .translate = translate_wrmsk_expstate,
+        .windowed_register_op = 0x3,
     }, {
         .name = "wsr.176",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){176},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.208",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){208},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.acchi",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ACCHI},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.acclo",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ACCLO},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.atomctl",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ATOMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.br",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){BR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.cacheattr",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CACHEATTR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ccompare0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CCOMPARE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ccompare1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CCOMPARE + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ccompare2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CCOMPARE + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ccount",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CCOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.configid0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CONFIGID0},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.configid1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CONFIGID1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.cpenable",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){CPENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.dbreaka0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.dbreaka1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.dbreakc0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DBREAKC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.dbreakc1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ddr",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.debugcause",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DEBUGCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.depc",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DEPC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.dtlbcfg",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){DTLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc3",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc4",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc5",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc6",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.epc7",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPC1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps3",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps4",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps5",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps6",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.eps7",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EPS2 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.exccause",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave3",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave4",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave5",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave6",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excsave7",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.excvaddr",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){EXCVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ibreaka0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){IBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ibreaka1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){IBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ibreakenable",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){IBREAKENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.icount",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ICOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.icountlevel",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ICOUNTLEVEL},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.intclear",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){INTCLEAR},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.intenable",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){INTENABLE},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.interrupt",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.intset",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.itlbcfg",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){ITLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.lbeg",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){LBEG},
+        .op_flags = XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.lcount",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){LCOUNT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.lend",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){LEND},
+        .op_flags = XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.litbase",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){LITBASE},
+        .op_flags = XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.m0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.m1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MR + 1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.m2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MR + 2},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.m3",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MR + 3},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.memctl",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MEMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.misc0",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MISC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.misc1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MISC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.misc2",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MISC + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.misc3",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MISC + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.mmid",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){MMID},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.prid",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){PRID},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ps",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){PS},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.ptevaddr",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){PTEVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.rasid",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){RASID},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.sar",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){SAR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.scompare1",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){SCOMPARE1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.vecbase",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){VECBASE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.windowbase",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){WINDOW_BASE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wsr.windowstart",
         .translate = translate_wsr,
+        .test_ill = test_ill_wsr,
         .par = (const uint32_t[]){WINDOW_START},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "wur.expstate",
         .translate = translate_wur,
         .par = (const uint32_t[]){EXPSTATE},
+        .windowed_register_op = 0x1,
     }, {
         .name = "wur.fcr",
         .translate = translate_wur,
         .par = (const uint32_t[]){FCR},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "wur.fsr",
         .translate = translate_wur,
         .par = (const uint32_t[]){FSR},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "wur.threadptr",
         .translate = translate_wur,
         .par = (const uint32_t[]){THREADPTR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xor",
         .translate = translate_xor,
+        .windowed_register_op = 0x7,
     }, {
         .name = "xorb",
         .translate = translate_boolean,
@@ -4248,307 +4794,540 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "xsr.176",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){176},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.208",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){208},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.acchi",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ACCHI},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.acclo",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ACCLO},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.atomctl",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ATOMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.br",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){BR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.cacheattr",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CACHEATTR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ccompare0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CCOMPARE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ccompare1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CCOMPARE + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ccompare2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CCOMPARE + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ccount",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CCOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.configid0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CONFIGID0},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.configid1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CONFIGID1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.cpenable",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){CPENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.dbreaka0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.dbreaka1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.dbreakc0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DBREAKC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.dbreakc1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ddr",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.debugcause",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DEBUGCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.depc",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DEPC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.dtlbcfg",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){DTLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc3",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc4",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc5",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc6",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.epc7",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPC1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps3",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps4",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps5",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps6",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.eps7",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EPS2 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.exccause",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCCAUSE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave3",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave4",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave5",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 4},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave6",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 5},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excsave7",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCSAVE1 + 6},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.excvaddr",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){EXCVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ibreaka0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){IBREAKA},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ibreaka1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){IBREAKA + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ibreakenable",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){IBREAKENABLE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.icount",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ICOUNT},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.icountlevel",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ICOUNTLEVEL},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.intclear",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){INTCLEAR},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.intenable",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){INTENABLE},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.interrupt",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.intset",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){INTSET},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_0 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.itlbcfg",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){ITLBCFG},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.lbeg",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){LBEG},
+        .op_flags = XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.lcount",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){LCOUNT},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.lend",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){LEND},
+        .op_flags = XTENSA_OP_EXIT_TB_0,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.litbase",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){LITBASE},
+        .op_flags = XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.m0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.m1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MR + 1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.m2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MR + 2},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.m3",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MR + 3},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.memctl",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MEMCTL},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.misc0",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MISC},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.misc1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MISC + 1},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.misc2",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MISC + 2},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.misc3",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){MISC + 3},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.prid",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){PRID},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ps",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){PS},
+        .op_flags =
+            XTENSA_OP_PRIVILEGED |
+            XTENSA_OP_EXIT_TB_M1 |
+            XTENSA_OP_CHECK_INTERRUPTS,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.ptevaddr",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){PTEVADDR},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.rasid",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){RASID},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.sar",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){SAR},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.scompare1",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){SCOMPARE1},
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.vecbase",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){VECBASE},
+        .op_flags = XTENSA_OP_PRIVILEGED,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.windowbase",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){WINDOW_BASE},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     }, {
         .name = "xsr.windowstart",
         .translate = translate_xsr,
+        .test_ill = test_ill_xsr,
         .par = (const uint32_t[]){WINDOW_START},
+        .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+        .windowed_register_op = 0x1,
     },
 };
 
@@ -4561,18 +5340,14 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = {
 static void translate_abs_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
 }
 
 static void translate_add_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_add_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_add_s(cpu_FR[arg[0]], cpu_env,
+                     cpu_FR[arg[1]], cpu_FR[arg[2]]);
 }
 
 enum {
@@ -4598,331 +5373,357 @@ static void translate_compare_s(DisasContext *dc, const uint32_t arg[],
         [COMPARE_OLE] = gen_helper_ole_s,
         [COMPARE_ULE] = gen_helper_ule_s,
     };
+    TCGv_i32 bit = tcg_const_i32(1 << arg[0]);
 
-    if (gen_check_cpenable(dc, 0)) {
-        TCGv_i32 bit = tcg_const_i32(1 << arg[0]);
-
-        helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]);
-        tcg_temp_free(bit);
-    }
+    helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]);
+    tcg_temp_free(bit);
 }
 
 static void translate_float_s(DisasContext *dc, const uint32_t arg[],
                               const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 scale = tcg_const_i32(-arg[2]);
+    TCGv_i32 scale = tcg_const_i32(-arg[2]);
 
-        if (par[0]) {
-            gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
-        } else {
-            gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
-        }
-        tcg_temp_free(scale);
+    if (par[0]) {
+        gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
+    } else {
+        gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale);
     }
+    tcg_temp_free(scale);
 }
 
 static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
-        TCGv_i32 scale = tcg_const_i32(arg[2]);
+    TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
+    TCGv_i32 scale = tcg_const_i32(arg[2]);
 
-        if (par[1]) {
-            gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]],
-                             rounding_mode, scale);
-        } else {
-            gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]],
-                            rounding_mode, scale);
-        }
-        tcg_temp_free(rounding_mode);
-        tcg_temp_free(scale);
+    if (par[1]) {
+        gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]],
+                         rounding_mode, scale);
+    } else {
+        gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]],
+                        rounding_mode, scale);
     }
+    tcg_temp_free(rounding_mode);
+    tcg_temp_free(scale);
 }
 
 static void translate_ldsti(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        if (par[0]) {
-            tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
-        } else {
-            tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
-        }
-        if (par[1]) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], addr);
-        }
-        tcg_temp_free(addr);
+    tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]);
+    gen_load_store_alignment(dc, 2, addr, false);
+    if (par[0]) {
+        tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
+    } else {
+        tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
     }
+    if (par[1]) {
+        tcg_gen_mov_i32(cpu_R[arg[1]], addr);
+    }
+    tcg_temp_free(addr);
 }
 
 static void translate_ldstx(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 addr = tcg_temp_new_i32();
+    TCGv_i32 addr = tcg_temp_new_i32();
 
-        tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]);
-        gen_load_store_alignment(dc, 2, addr, false);
-        if (par[0]) {
-            tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
-        } else {
-            tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
-        }
-        if (par[1]) {
-            tcg_gen_mov_i32(cpu_R[arg[1]], addr);
-        }
-        tcg_temp_free(addr);
+    tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]);
+    gen_load_store_alignment(dc, 2, addr, false);
+    if (par[0]) {
+        tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring);
+    } else {
+        tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring);
+    }
+    if (par[1]) {
+        tcg_gen_mov_i32(cpu_R[arg[1]], addr);
     }
+    tcg_temp_free(addr);
 }
 
 static void translate_madd_s(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_madd_s(cpu_FR[arg[0]], cpu_env,
-                          cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_madd_s(cpu_FR[arg[0]], cpu_env,
+                      cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
 }
 
 static void translate_mov_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]);
 }
 
 static void translate_movcond_s(DisasContext *dc, const uint32_t arg[],
                                 const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) {
-        TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 zero = tcg_const_i32(0);
 
-        tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]],
-                            cpu_R[arg[2]], zero,
-                            cpu_FR[arg[1]], cpu_FR[arg[0]]);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]],
+                        cpu_R[arg[2]], zero,
+                        cpu_FR[arg[1]], cpu_FR[arg[0]]);
+    tcg_temp_free(zero);
 }
 
 static void translate_movp_s(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        TCGv_i32 zero = tcg_const_i32(0);
-        TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 zero = tcg_const_i32(0);
+    TCGv_i32 tmp = tcg_temp_new_i32();
 
-        tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
-        tcg_gen_movcond_i32(par[0],
-                            cpu_FR[arg[0]], tmp, zero,
-                            cpu_FR[arg[1]], cpu_FR[arg[0]]);
-        tcg_temp_free(tmp);
-        tcg_temp_free(zero);
-    }
+    tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]);
+    tcg_gen_movcond_i32(par[0],
+                        cpu_FR[arg[0]], tmp, zero,
+                        cpu_FR[arg[1]], cpu_FR[arg[0]]);
+    tcg_temp_free(tmp);
+    tcg_temp_free(zero);
 }
 
 static void translate_mul_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_mul_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_mul_s(cpu_FR[arg[0]], cpu_env,
+                     cpu_FR[arg[1]], cpu_FR[arg[2]]);
 }
 
 static void translate_msub_s(DisasContext *dc, const uint32_t arg[],
                              const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_msub_s(cpu_FR[arg[0]], cpu_env,
-                          cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_msub_s(cpu_FR[arg[0]], cpu_env,
+                      cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]);
 }
 
 static void translate_neg_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
-    }
+    gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]);
 }
 
 static void translate_rfr_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[0]) &&
-        gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]);
-    }
+    tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]);
 }
 
 static void translate_sub_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_check_cpenable(dc, 0)) {
-        gen_helper_sub_s(cpu_FR[arg[0]], cpu_env,
-                         cpu_FR[arg[1]], cpu_FR[arg[2]]);
-    }
+    gen_helper_sub_s(cpu_FR[arg[0]], cpu_env,
+                     cpu_FR[arg[1]], cpu_FR[arg[2]]);
 }
 
 static void translate_wfr_s(DisasContext *dc, const uint32_t arg[],
                             const uint32_t par[])
 {
-    if (gen_window_check1(dc, arg[1]) &&
-        gen_check_cpenable(dc, 0)) {
-        tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]);
-    }
+    tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]);
 }
 
 static const XtensaOpcodeOps fpu2000_ops[] = {
     {
         .name = "abs.s",
         .translate = translate_abs_s,
+        .coprocessor = 0x1,
     }, {
         .name = "add.s",
         .translate = translate_add_s,
+        .coprocessor = 0x1,
     }, {
         .name = "ceil.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_up, false},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "float.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){false},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "floor.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_down, false},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "lsi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, false},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "lsiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){false, true},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "lsx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, false},
+        .windowed_register_op = 0x6,
+        .coprocessor = 0x1,
     }, {
         .name = "lsxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){false, true},
+        .windowed_register_op = 0x6,
+        .coprocessor = 0x1,
     }, {
         .name = "madd.s",
         .translate = translate_madd_s,
+        .coprocessor = 0x1,
     }, {
         .name = "mov.s",
         .translate = translate_mov_s,
+        .coprocessor = 0x1,
     }, {
         .name = "moveqz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .windowed_register_op = 0x4,
+        .coprocessor = 0x1,
     }, {
         .name = "movf.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_EQ},
+        .coprocessor = 0x1,
     }, {
         .name = "movgez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_GE},
+        .windowed_register_op = 0x4,
+        .coprocessor = 0x1,
     }, {
         .name = "movltz.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_LT},
+        .windowed_register_op = 0x4,
+        .coprocessor = 0x1,
     }, {
         .name = "movnez.s",
         .translate = translate_movcond_s,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .windowed_register_op = 0x4,
+        .coprocessor = 0x1,
     }, {
         .name = "movt.s",
         .translate = translate_movp_s,
         .par = (const uint32_t[]){TCG_COND_NE},
+        .coprocessor = 0x1,
     }, {
         .name = "msub.s",
         .translate = translate_msub_s,
+        .coprocessor = 0x1,
     }, {
         .name = "mul.s",
         .translate = translate_mul_s,
+        .coprocessor = 0x1,
     }, {
         .name = "neg.s",
         .translate = translate_neg_s,
+        .coprocessor = 0x1,
     }, {
         .name = "oeq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OEQ},
+        .coprocessor = 0x1,
     }, {
         .name = "ole.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLE},
+        .coprocessor = 0x1,
     }, {
         .name = "olt.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_OLT},
+        .coprocessor = 0x1,
     }, {
         .name = "rfr",
         .translate = translate_rfr_s,
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "round.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_nearest_even, false},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "ssi",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, false},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "ssiu",
         .translate = translate_ldsti,
         .par = (const uint32_t[]){true, true},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "ssx",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, false},
+        .windowed_register_op = 0x6,
+        .coprocessor = 0x1,
     }, {
         .name = "ssxu",
         .translate = translate_ldstx,
         .par = (const uint32_t[]){true, true},
+        .windowed_register_op = 0x6,
+        .coprocessor = 0x1,
     }, {
         .name = "sub.s",
         .translate = translate_sub_s,
+        .coprocessor = 0x1,
     }, {
         .name = "trunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, false},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "ueq.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UEQ},
+        .coprocessor = 0x1,
     }, {
         .name = "ufloat.s",
         .translate = translate_float_s,
         .par = (const uint32_t[]){true},
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     }, {
         .name = "ule.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULE},
+        .coprocessor = 0x1,
     }, {
         .name = "ult.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_ULT},
+        .coprocessor = 0x1,
     }, {
         .name = "un.s",
         .translate = translate_compare_s,
         .par = (const uint32_t[]){COMPARE_UN},
+        .coprocessor = 0x1,
     }, {
         .name = "utrunc.s",
         .translate = translate_ftoi_s,
         .par = (const uint32_t[]){float_round_to_zero, true},
+        .windowed_register_op = 0x1,
+        .coprocessor = 0x1,
     }, {
         .name = "wfr",
         .translate = translate_wfr_s,
+        .windowed_register_op = 0x2,
+        .coprocessor = 0x1,
     },
 };