diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2017-11-02 15:05:56 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-01-09 09:55:39 -0800 |
| commit | c5ac936e5e8356cf6bba8e39519a273ab0fc6fed (patch) | |
| tree | f84c78f121bf4db1e0c3c97329c5936b95bb1ff7 /target | |
| parent | e98727417aa639024af9d17650f8811dc408885c (diff) | |
target/xtensa: implement const16
const16 is an opcode that shifts 16 lower bits of an address register
to the 16 upper bits and puts its immediate operand into the lower 16
bits. It is not controlled by an Xtensa option and doesn't have a fixed
opcode.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/xtensa/translate.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 6f26e42a2b..4bdfcd24d0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1521,6 +1521,17 @@ static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); } +static void translate_const16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 c = tcg_const_i32(arg[1]); + + tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); + tcg_temp_free(c); + } +} + /* par[0]: privileged, par[1]: check memory access */ static void translate_dcache(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) @@ -2737,6 +2748,9 @@ static const XtensaOpcodeOps core_ops[] = { .name = "clrb_expstate", .translate = translate_clrb_expstate, }, { + .name = "const16", + .translate = translate_const16, + }, { .name = "depbits", .translate = translate_depbits, }, { |