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authorAleksandar Markovic <amarkovic@wavecomp.com>2019-07-15 22:00:44 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2019-07-15 22:21:56 +0200
commitab8c34105a0ddd0c05159fb76919a18de8df4e8f (patch)
treef6d04b60cc6156b25c4ab32d8ba063bce5ae89d3 /target
parent5ea8ec2fcf57cb9af24ad2cf17b4d64adb03afdf (diff)
target/mips: Add missing 'break' for a case of MTHC0 handling
This was found by GCC 8.3 static analysis. Fixes: 5fb2dcd1792 Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target')
-rw-r--r--target/mips/translate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96f141cdf..cce1f12590 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6745,6 +6745,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
+ break;
case CP0_REGISTER_17:
switch (sel) {
case 0: