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authorPavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>2022-06-20 15:05:27 +0300
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-07-12 22:30:12 +0200
commit5e806fb00214142377bcbf7da8e79c62556d142c (patch)
treee2a7d9e31abfa55c268579cdac95f55110b68267 /target
parent72d680e4083a75c55d89c55f799cbe870ebbc7a5 (diff)
target/mips: implement Octeon-specific BBIT instructions
This patch introduces Octeon-specific decoder and implements check-bit-and-jump instructions. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target')
-rw-r--r--target/mips/tcg/octeon.decode9
-rw-r--r--target/mips/tcg/octeon_translate.c30
2 files changed, 39 insertions, 0 deletions
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index b21c735a6c..8062715578 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -4,3 +4,12 @@
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
+
+# Branch on bit set or clear
+# BBIT0 110010 ..... ..... ................
+# BBIT032 110110 ..... ..... ................
+# BBIT1 111010 ..... ..... ................
+# BBIT132 111110 ..... ..... ................
+
+%bbit_p 28:1 16:5
+BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 8b5eb1a823..1558f74a8e 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -14,3 +14,33 @@
/* Include the auto-generated decoder. */
#include "decode-octeon.c.inc"
+
+static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
+{
+ TCGv p;
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
+ TARGET_FMT_lx "\n", ctx->base.pc_next);
+ generate_exception_end(ctx, EXCP_RI);
+ return true;
+ }
+
+ /* Load needed operands */
+ TCGv t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+
+ p = tcg_constant_tl(1ULL << a->p);
+ if (a->set) {
+ tcg_gen_and_tl(bcond, p, t0);
+ } else {
+ tcg_gen_andc_tl(bcond, p, t0);
+ }
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ tcg_temp_free(t0);
+ return true;
+}