diff options
author | Yongbok Kim <yongbok.kim@mips.com> | 2018-08-02 16:16:14 +0200 |
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committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
commit | 4d18232ca0f903df099d243ccfe28b0e545dc92d (patch) | |
tree | 49849e15115059cdd29d68ed7bbe399917be09f8 /target | |
parent | c0280983034627a336248409711e969eb2ea8325 (diff) |
target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/mips/translate.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index cbe3779ee1..8bc08f742e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17438,8 +17438,39 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_MOVEP: - break; case NM_MOVEPREV: + { + static const int gpr2reg1[] = {4, 5, 6, 7}; + static const int gpr2reg2[] = {5, 6, 7, 8}; + int re; + int rd2 = extract32(ctx->opcode, 3, 1) << 1 | + extract32(ctx->opcode, 8, 1); + int r1 = gpr2reg1[rd2]; + int r2 = gpr2reg2[rd2]; + int r3 = extract32(ctx->opcode, 4, 1) << 3 | + extract32(ctx->opcode, 0, 3); + int r4 = extract32(ctx->opcode, 9, 1) << 3 | + extract32(ctx->opcode, 5, 3); + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + if (op == NM_MOVEP) { + rd = r1; + re = r2; + rs = decode_gpr_gpr4_zero(r3); + rt = decode_gpr_gpr4_zero(r4); + } else { + rd = decode_gpr_gpr4(r3); + re = decode_gpr_gpr4(r4); + rs = r1; + rt = r2; + } + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_mov_tl(cpu_gpr[rd], t0); + tcg_gen_mov_tl(cpu_gpr[re], t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } break; default: return decode_nanomips_32_48_opc(env, ctx); |