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authorRichard Henderson <richard.henderson@linaro.org>2019-02-15 09:56:41 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-15 09:56:41 +0000
commit18aaa59c622208743565307668a2100ab24f7de9 (patch)
treecff4b27a02d325b0f26da5be2c5f23ed424ebe13 /target
parent55a889456ef78f3f9b8eae9846c2f1453b1dd77b (diff)
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190209033847.9014-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/helper.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 28e45f0f0b..d4b7eca30a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12707,7 +12707,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
int i;
uint32_t fpscr;
- fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
@@ -12749,7 +12749,7 @@ static inline int vfp_exceptbits_to_host(int target_bits)
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
int i;
- uint32_t changed;
+ uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
@@ -12758,12 +12758,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
/*
* We don't implement trapped exception handling, so the
- * trap enable bits are all RAZ/WI (not RES0!)
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
+ *
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
+ * (which are stored in fp_status), and the other RES0 bits
+ * in between, then we clear all of the low 16 bits.
*/
- val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE);
-
- changed = env->vfp.xregs[ARM_VFP_FPSCR];
- env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000;
env->vfp.vec_len = (val >> 16) & 7;
env->vfp.vec_stride = (val >> 20) & 3;