diff options
| author | Stafford Horne <shorne@gmail.com> | 2017-06-18 01:50:06 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-10-21 06:35:47 +0900 |
| commit | 8c949951ed257567303c3d3b83bcd876b53d79e5 (patch) | |
| tree | 39a29ce409d4c834b13d0f65afaee8694e283c49 /target | |
| parent | 0ca9fa2e3c2d072ef7546190976e326ff2673a33 (diff) | |
target/openrisc: Make coreid and numcores variable
Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.
Multicore support is now being added so these registers need to have
configured values.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/openrisc/sys_helper.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index abdef5d6a5..dc6e5cc7f2 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" +#include "sysemu/sysemu.h" #define TO_SPR(group, number) (((group) << 11) + (number)) @@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->esr; case TO_SPR(0, 128): /* COREID */ - return 0; + return cpu->parent_obj.cpu_index; case TO_SPR(0, 129): /* NUMCORES */ - return 1; + return max_cpus; case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx = (spr - 1024); |