diff options
| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2017-02-27 10:28:01 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-03-01 11:23:39 +1100 |
| commit | b63d043418f76229a3637842cc1777280b695df1 (patch) | |
| tree | 202e72171d6591c25bb43ae3ffbeb42ce0c26665 /target | |
| parent | c44027ffb91e7eb335f5a4d418906460044796b9 (diff) | |
target/ppc: add mcrxrx instruction
mcrxrx: Move to CR from XER Extended
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/translate.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 982e66fadb..6e6868b7a0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3819,6 +3819,28 @@ static void gen_mcrxr(DisasContext *ctx) tcg_gen_movi_tl(cpu_ca, 0); } +#ifdef TARGET_PPC64 +/* mcrxrx */ +static void gen_mcrxrx(DisasContext *ctx) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; + + /* copy OV and OV32 */ + tcg_gen_shli_tl(t0, cpu_ov, 1); + tcg_gen_or_tl(t0, t0, cpu_ov32); + tcg_gen_shli_tl(t0, t0, 2); + /* copy CA and CA32 */ + tcg_gen_shli_tl(t1, cpu_ca, 1); + tcg_gen_or_tl(t1, t1, cpu_ca32); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_trunc_tl_i32(dst, t0); + tcg_temp_free(t0); + tcg_temp_free(t1); +} +#endif + /* mfcr mfocrf */ static void gen_mfcr(DisasContext *ctx) { @@ -6488,6 +6510,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |