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authorRichard Henderson <richard.henderson@linaro.org>2023-02-24 21:53:49 -1000
committerRichard Henderson <richard.henderson@linaro.org>2023-03-05 13:44:08 -0800
commita49f3a2e1966096c745b9fe2749e0facc39dbaea (patch)
tree1766b3fe555b0723b1eda05336ea6abcd1a5c709 /target
parentd47913c104c6e9569792c4bbaf57e11d9b2f5e7f (diff)
target/xtensa: Drop reset_sar_tracker
Translators are no longer required to free tcg temporaries. Remove sar_m32_allocated, as sar_m32 non-null is equivalent. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/xtensa/translate.c14
1 files changed, 2 insertions, 12 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4af0650deb..910350dec6 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -57,7 +57,6 @@ struct DisasContext {
bool sar_5bit;
bool sar_m32_5bit;
- bool sar_m32_allocated;
TCGv_i32 sar_m32;
unsigned window;
@@ -284,14 +283,7 @@ static void init_sar_tracker(DisasContext *dc)
{
dc->sar_5bit = false;
dc->sar_m32_5bit = false;
- dc->sar_m32_allocated = false;
-}
-
-static void reset_sar_tracker(DisasContext *dc)
-{
- if (dc->sar_m32_allocated) {
- tcg_temp_free(dc->sar_m32);
- }
+ dc->sar_m32 = NULL;
}
static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
@@ -306,9 +298,8 @@ static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
- if (!dc->sar_m32_allocated) {
+ if (!dc->sar_m32) {
dc->sar_m32 = tcg_temp_new_i32();
- dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
@@ -1247,7 +1238,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- reset_sar_tracker(dc);
if (dc->icount) {
tcg_temp_free(dc->next_icount);
}