diff options
| author | Dimitrije Nikolic <dnikolic@wavecomp.com> | 2018-08-20 12:14:23 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
| commit | ab77fc611bf004dfd25ecad5b2c11261e32012e9 (patch) | |
| tree | 0c36a557d9254dae4a06b9e8617b7ebb74faafda /target | |
| parent | 8f1d9b6d63978b80971b15fef16636f454241879 (diff) | |
target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.
Reviewed-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
Signed-off-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 4b1bb18316..10475a6c6b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1449,6 +1449,8 @@ typedef struct DisasContext { uint32_t opcode; int insn_flags; int32_t CP0_Config1; + int32_t CP0_Config3; + int32_t CP0_Config5; /* Routine used to access memory */ int mem_idx; TCGMemOp default_tcg_memop_mask; @@ -23307,6 +23309,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->saved_pc = -1; ctx->insn_flags = env->insn_flags; ctx->CP0_Config1 = env->CP0_Config1; + ctx->CP0_Config3 = env->CP0_Config3; + ctx->CP0_Config5 = env->CP0_Config5; ctx->btarget = 0; ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; |