diff options
| author | Kito Cheng <kito.cheng@gmail.com> | 2019-03-16 01:20:46 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:14:39 -0700 |
| commit | 5836c3eccedb6dfab16b8f606f2de24b8938b69c (patch) | |
| tree | 06b0788af46c10271d0d2781acb90a7a8cfebbcf /target | |
| parent | c02b78c7b4cecfe0a027abff8ecc3ec02e8b4a53 (diff) | |
RISC-V: linux-user support for RVE ABI
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.
Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Co-authored-by: Kito Cheng <kito.cheng@gmail.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.h | 4 | ||||
| -rw-r--r-- | target/riscv/cpu_user.h | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df43a0898d..20bce8742e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -123,6 +123,10 @@ struct CPURISCVState { uint32_t features; +#ifdef CONFIG_USER_ONLY + uint32_t elf_flags; +#endif + #ifndef CONFIG_USER_ONLY target_ulong priv; target_ulong resetvec; diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h index c2199610ab..52d380aa98 100644 --- a/target/riscv/cpu_user.h +++ b/target/riscv/cpu_user.h @@ -10,4 +10,5 @@ #define xA4 14 #define xA5 15 #define xA6 16 -#define xA7 17 /* syscall number goes here */ +#define xA7 17 /* syscall number for RVI ABI */ +#define xT0 5 /* syscall number for RVE ABI */ |