diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-24 19:50:43 -1000 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-05 13:44:08 -0800 |
commit | c447a8685fc9bb2d6fd56024c879e1245cee9055 (patch) | |
tree | 492dd27624879f7708f0a2f67bdd3b3077d4b9d4 /target | |
parent | b304346e8b812994521eae75282773ae314635e4 (diff) |
target/nios2: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/nios2/translate.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 140bc31017..6610e22236 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -233,7 +233,6 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call) tcg_gen_andi_tl(test, dest, 3); tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l); - tcg_temp_free(test); tcg_gen_mov_tl(cpu_pc, dest); if (is_call) { @@ -300,7 +299,6 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags) tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - tcg_temp_free(addr); } /* Store instructions */ @@ -312,7 +310,6 @@ static void gen_stx(DisasContext *dc, uint32_t code, uint32_t flags) TCGv addr = tcg_temp_new(); tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags); - tcg_temp_free(addr); } /* Branch instructions */ @@ -500,7 +497,6 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); - tcg_temp_free(tmp); } else { gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA)); } @@ -530,7 +526,6 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) TCGv tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); - tcg_temp_free(tmp); dc->base.is_jmp = DISAS_NORETURN; #endif @@ -597,8 +592,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING])); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE])); tcg_gen_and_tl(dest, t1, t2); - tcg_temp_free(t1); - tcg_temp_free(t2); break; default: tcg_gen_ld_tl(dest, cpu_env, @@ -662,11 +655,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) tcg_gen_ld_tl(o, cpu_env, ofs); tcg_gen_andi_tl(o, o, ro); tcg_gen_or_tl(n, n, o); - tcg_temp_free(o); } tcg_gen_st_tl(n, cpu_env, ofs); - tcg_temp_free(n); } break; } @@ -753,7 +744,6 @@ static void do_rr_mul_high(DisasContext *dc, uint32_t insn, GenFn4 *fn) fn(discard, dest_gpr(dc, instr.c), load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_temp_free(discard); } #define gen_rr_mul_high(fname, insn) \ @@ -771,7 +761,6 @@ static void do_rr_shift(DisasContext *dc, uint32_t insn, GenFn3 *fn) tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31); fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh); - tcg_temp_free(sh); } #define gen_rr_shift(fname, insn) \ @@ -990,10 +979,6 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) instr = &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->sink) { - tcg_temp_free(dc->sink); - } } static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) |