diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-01-14 13:32:06 -1000 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-03-29 10:20:04 +0300 |
| commit | f163cf6be4b7b51f7327d264ea2572f8b495d287 (patch) | |
| tree | ca8eda9d320cf4de01588a77d74d02b8d04f7590 /target | |
| parent | c45d10f6557b4fdae3e97f1326429bb85f5a8717 (diff) | |
target/i386: Fix BZHI instruction
We did not correctly handle N >= operand size.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230114233206.3118472-1-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 9ad2ba6e8e7fc195d0dd0b76ab38bd2fceb1bdd4)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/tcg/emit.c.inc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 0d7c6e80ae..7296f3952c 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1145,20 +1145,20 @@ static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) static void gen_BZHI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { MemOp ot = decode->op[0].ot; - TCGv bound; + TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); + TCGv zero = tcg_constant_tl(0); + TCGv mone = tcg_constant_tl(-1); - tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]); - bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); + tcg_gen_ext8u_tl(s->T1, s->T1); /* * Note that since we're using BMILG (in order to get O * cleared) we need to store the inverse into C. */ - tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src, s->T1, bound); - tcg_gen_movcond_tl(TCG_COND_GT, s->T1, s->T1, bound, bound, s->T1); + tcg_gen_setcond_tl(TCG_COND_LEU, cpu_cc_src, s->T1, bound); - tcg_gen_movi_tl(s->A0, -1); - tcg_gen_shl_tl(s->A0, s->A0, s->T1); + tcg_gen_shl_tl(s->A0, mone, s->T1); + tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); tcg_gen_andc_tl(s->T0, s->T0, s->A0); gen_op_update1_cc(s); |