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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-07-22 15:16:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-22 15:16:48 +0100 |
| commit | 23da9e297b4120ca9702cabec91599a44255fe96 (patch) | |
| tree | 8eb09f5aa4898bbf40883f34a1be0a65e55d0036 /target | |
| parent | 9d2e1fcd14c2bae5be1992214a03c0ddff714c80 (diff) | |
| parent | ddb45afbfbc639365d6c934e4e29f6de5e5e2a0e (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190722' into staging
target-arm queue:
* target/arm: Add missing break statement for Hypervisor Trap Exception
(fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
* hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
* target/arm: Limit ID register assertions to TCG
* configure: Clarify URL to source downloads
* contrib/elf2dmp: Build download.o with CURL_CFLAGS
# gpg: Signature made Mon 22 Jul 2019 14:13:31 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190722:
contrib/elf2dmp: Build download.o with CURL_CFLAGS
configure: Clarify URL to source downloads
target/arm: Limit ID register assertions to TCG
hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
target/arm: Add missing break statement for Hypervisor Trap Exception
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 7 | ||||
| -rw-r--r-- | target/arm/helper.c | 1 |
2 files changed, 6 insertions, 2 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1959467fdc..9eb40ff755 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1369,6 +1369,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * There exist AArch64 cpus without AArch32 support. When KVM * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. + * As a general principle, we also do not make ID register + * consistency checks anywhere unless using TCG, because only + * for TCG would a consistency-check failure be a QEMU bug. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); @@ -1383,7 +1386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1409,7 +1412,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 20f8728be1..b74c23a9bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7956,6 +7956,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) break; case EXCP_HYP_TRAP: addr = 0x14; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } |