diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-27 11:18:59 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-30 17:05:11 +0100 |
| commit | df9024760efa9a32e24629eb80665c8c4ec5f145 (patch) | |
| tree | ad42fb3445d3dcd389ee3feeb2f9d4d059424694 /target | |
| parent | d961b3e40bd2c98de8bac554597e905daab13b91 (diff) | |
target/arm: Remove assert in trans_FCMLA_zzxz
Since 636ddeb15c0, we do not require rd == ra.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-107-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-sve.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 886cf539a5..436d09b928 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4027,8 +4027,6 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a) NULL, }; - tcg_debug_assert(a->rd == a->ra); - return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); |