diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:51:52 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | a3637e8882f9dbb00036ff77a88b841bd2580900 (patch) | |
| tree | ed5b8dda8291d86f3df4abbe721731945344ab72 /target | |
| parent | d5b1223ac1ddf8f706f5e6feaaa526df8287f8b1 (diff) | |
target/arm: Add PSTATE.{SM,ZA} to TB flags
These are required to determine if various insns
are allowed to issue.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.h | 2 | ||||
| -rw-r--r-- | target/arm/helper.c | 4 | ||||
| -rw-r--r-- | target/arm/translate-a64.c | 2 | ||||
| -rw-r--r-- | target/arm/translate.h | 4 |
4 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dec52c6c3b..05d369e690 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3160,6 +3160,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) /* * Helpers for using the above. diff --git a/target/arm/helper.c b/target/arm/helper.c index bbd04fbd67..e06c054c3d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11335,6 +11335,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + DP_TBFLAG_A64(flags, PSTATE_SM, 1); + } + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8f609f46b6..5cf4a283ba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14630,6 +14630,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ata = EX_TBFLAG_A64(tb_flags, ATA); dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); + dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); + dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; diff --git a/target/arm/translate.h b/target/arm/translate.h index c88c953325..93766649f7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -97,6 +97,10 @@ typedef struct DisasContext { bool align_mem; /* True if PSTATE.IL is set */ bool pstate_il; + /* True if PSTATE.SM is set. */ + bool pstate_sm; + /* True if PSTATE.ZA is set. */ + bool pstate_za; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* |