diff options
author | David Hildenbrand <david@redhat.com> | 2019-02-18 13:27:00 +0100 |
---|---|---|
committer | Cornelia Huck <cohuck@redhat.com> | 2019-03-04 11:49:31 +0100 |
commit | 6d6ad1d14e2fdbc693524dbd721ef33d0adb9473 (patch) | |
tree | 19fe77e36fd72b1d06215816c06f0d07f13e2382 /target | |
parent | fcb9e9f2a1b229b834e4133f626c4f40b43f7b9d (diff) |
s390x/tcg: Hide IEEE underflows in some scenarios
IEEE underflows are not reported when the mask bit is off and we don't
also have an inexact exception.
z14 PoP, 9-20, "IEEE Underflow":
An IEEE-underflow exception is recognized for an
IEEE target when the tininess condition exists and
either: (1) the IEEE-underflow mask bit in the FPC
register is zero and the result value is inexact, or (2)
the IEEE-underflow mask bit in the FPC register is
one.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190218122710.23639-6-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target')
-rw-r--r-- | target/s390x/fpu_helper.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index dcad9c367a..64efab72a4 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -64,6 +64,19 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr) s390_exc = s390_softfloat_exc_to_ieee(qemu_exc); /* + * IEEE-Underflow exception recognition exists if a tininess condition + * (underflow) exists and + * - The mask bit in the FPC is zero and the result is inexact + * - The mask bit in the FPC is one + * So tininess conditions that are not inexact don't trigger any + * underflow action in case the mask bit is not one. + */ + if (!(s390_exc & S390_IEEE_MASK_INEXACT) && + !((env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW)) { + s390_exc &= ~S390_IEEE_MASK_UNDERFLOW; + } + + /* * FIXME: * 1. Right now, all inexact conditions are inidicated as * "truncated" (0) and never as "incremented" (1) in the DXC. |