diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-09-11 18:54:28 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-09-14 12:00:21 -0700 |
| commit | 17b3c353e6aa4627d2418714cf2431853da45e31 (patch) | |
| tree | 82afb89f796b1f3aa2777649b905004a6b07a0a8 /target | |
| parent | f725245c527c96e4333e9bf3ed38635ee8c9fcbc (diff) | |
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210911165434.531552-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 2 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_helper.c | 5 |
3 files changed, 2 insertions, 7 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579..13575c1408 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..e735e53e26 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); @@ -362,6 +361,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..701858d670 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } -#endif bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return true; } } -#endif return false; } -#if !defined(CONFIG_USER_ONLY) - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { |