diff options
| author | Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> | 2017-01-10 00:10:11 -0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-01-31 10:10:14 +1100 |
| commit | a49a95e9e4dc2652cdc8a1e4fb1bfb66dba2e1d8 (patch) | |
| tree | 4e675631154e71c1fcb87c112ecb9a1d97d27f23 /target | |
| parent | e04797f79e48b5410457ec093249676585361de0 (diff) | |
ppc: Implement bcdus. instruction
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/helper.h | 1 | ||||
| -rw-r--r-- | target/ppc/int_helper.c | 41 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-impl.inc.c | 3 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-ops.inc.c | 2 |
4 files changed, 46 insertions, 1 deletions
diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 26edbf92a5..161d537987 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -394,6 +394,7 @@ DEF_HELPER_3(bcdctsq, i32, avr, avr, i32) DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32) DEF_HELPER_4(bcds, i32, avr, avr, avr, i32) +DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xsaddqp, void, env, i32) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 5f53710c07..9d88352e2f 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -3102,6 +3102,47 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +{ + int cr; + int i; + int invalid = 0; + bool ox_flag = false; + ppc_avr_t ret = *b; + + for (i = 0; i < 32; i++) { + bcd_get_digit(b, i, &invalid); + + if (unlikely(invalid)) { + return CRF_SO; + } + } + +#if defined(HOST_WORDS_BIGENDIAN) + i = a->s8[7]; +#else + i = a->s8[8]; +#endif + if (i >= 32) { + ox_flag = true; + ret.u64[LO_IDX] = ret.u64[HI_IDX] = 0; + } else if (i <= -32) { + ret.u64[LO_IDX] = ret.u64[HI_IDX] = 0; + } else if (i > 0) { + ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag); + } else { + urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4); + } + *r = ret; + + cr = bcd_cmp_zero(r); + if (ox_flag) { + cr |= CRF_SO; + } + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 84ebb7e020..fc54881fb8 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -1017,6 +1017,7 @@ GEN_BCD2(bcdctsq) GEN_BCD2(bcdsetsgn) GEN_BCD(bcdcpsgn); GEN_BCD(bcds); +GEN_BCD(bcdus); static void gen_xpnd04_1(DisasContext *ctx) { @@ -1093,6 +1094,8 @@ GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ bcdcpsgn, PPC_NONE, PPC2_ISA300) GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ bcds, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ + bcdus, PPC_NONE, PPC2_ISA300) static void gen_vsbox(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index 7b4b0096d6..cdd3abe600 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -61,7 +61,7 @@ GEN_VXFORM(vadduwm, 0, 2), GEN_VXFORM_207(vaddudm, 0, 3), GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vsubuwm, 0, 18), +GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM(vmaxub, 1, 0), |