diff options
author | Helge Deller <deller@gmx.de> | 2023-08-07 11:32:09 +0200 |
---|---|---|
committer | Helge Deller <deller@gmx.de> | 2023-08-25 15:57:49 +0200 |
commit | c01e5dfb9a5b7a4c044e5da8840b6bc1175e5839 (patch) | |
tree | e04b94aac8be3bbefba7597a259cc9559c361d43 /target | |
parent | c400b6ed877213ad3d87d0e27f260401a9194c7c (diff) |
target/hppa: Add privilege to MMU index conversion helpers
Add two macros which convert privilege level to/from MMU index:
- PRIV_TO_MMU_IDX(priv)
returns the MMU index for the given privilege level
- MMU_IDX_TO_PRIV(mmu_idx)
returns the corresponding privilege level for this MMU index
The introduction of those macros make the code easier to read and
will help to improve performance in follow-up patch.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/hppa/cpu.h | 5 | ||||
-rw-r--r-- | target/hppa/translate.c | 9 |
2 files changed, 9 insertions, 5 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6c5b0e67c8..50b513f0ea 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,6 +36,9 @@ #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 +#define PRIV_TO_MMU_IDX(priv) (priv) +#define MMU_IDX_TO_PRIV(mmu_idx) (mmu_idx) + #define TARGET_INSN_START_EXTRA_WORDS 1 /* Hardware exceptions, interrupts, faults, and traps. */ @@ -236,7 +239,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) return MMU_USER_IDX; #else if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return env->iaoq_f & 3; + return PRIV_TO_MMU_IDX(env->iaoq_f & 3); } return MMU_PHYS_IDX; /* mmu disabled */ #endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d66fcb3e6a..e3af668252 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4057,14 +4057,15 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; #ifdef CONFIG_USER_ONLY - ctx->privilege = MMU_USER_IDX; + ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; - ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; + ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); + ctx->mmu_idx = (ctx->tb_flags & PSW_D ? + PRIV_TO_MMU_IDX(ctx->privilege) : MMU_PHYS_IDX); /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base = ctx->base.tb->cs_base; |