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authorFrank Chang <frank.chang@sifive.com>2022-09-18 16:32:44 +0800
committerAlistair Francis <alistair@alistair23.me>2022-09-27 07:04:38 +1000
commit9e37653b5c73d8e43013ed78ee9d7644f23d146c (patch)
tree002091a33f4987afccfadaf07dc98a848842edb6 /target
parenta06fded82e9edc471dbbe4321f856040b996b54c (diff)
target/riscv: Check the correct exception cause in vector GDB stub
After RISCVException enum is introduced, riscv_csrrw_debug() returns RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub should check the result against RISCV_EXCP_NONE instead of value 0. Otherwise, 'E14' packet would be incorrectly reported for vector CSRs when using "info reg vector" GDB command. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220918083245.13028-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/gdbstub.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 9974b7aac6..6e7bbdbd5e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -183,7 +183,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
target_ulong val = 0;
int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return gdb_get_regl(buf, val);
}
@@ -210,7 +210,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
target_ulong val = ldtul_p(mem_buf);
int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return sizeof(target_ulong);
}