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authorClaudio Fontana <cfontana@suse.de>2020-08-19 13:17:19 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2020-10-05 16:41:22 +0200
commit740b175973427bcfa32ad894bb1f83b96d184c28 (patch)
tree3613e83be5fd8620b369479b98e6ede5d5746a9a /target
parent0ac0b47c44b4be6cbce26777a1a5968cc8f025a5 (diff)
cpu-timers, icount: new modules
refactoring of cpus.c continues with cpu timer state extraction. cpu-timers: responsible for the softmmu cpu timers state, including cpu clocks and ticks. icount: counts the TCG instructions executed. As such it is specific to the TCG accelerator. Therefore, it is built only under CONFIG_TCG. One complication is due to qtest, which uses an icount field to warp time as part of qtest (qtest_clock_warp). In order to solve this problem, provide a separate counter for qtest. This requires fixing assumptions scattered in the code that qtest_enabled() implies icount_enabled(), checking each specific case. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [remove redundant initialization with qemu_spice_init] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [fix lingering calls to icount_get] Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/alpha/translate.c3
-rw-r--r--target/arm/helper.c3
-rw-r--r--target/riscv/csr.c4
3 files changed, 6 insertions, 4 deletions
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 8870284f57..36be602179 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "sysemu/cpus.h"
+#include "sysemu/cpu-timers.h"
#include "disas/disas.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
@@ -1329,7 +1330,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
case 249: /* VMTIME */
helper = gen_helper_get_vmtime;
do_helper:
- if (use_icount) {
+ if (icount_enabled()) {
gen_io_start();
helper(va);
return DISAS_PC_STALE;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b394db394a..b0bc4aa534 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -24,6 +24,7 @@
#include "hw/irq.h"
#include "hw/semihosting/semihost.h"
#include "sysemu/cpus.h"
+#include "sysemu/cpu-timers.h"
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"
#include "qemu/range.h"
@@ -1206,7 +1207,7 @@ static int64_t cycles_ns_per(uint64_t cycles)
static bool instructions_supported(CPUARMState *env)
{
- return use_icount == 1 /* Precise instruction counting */;
+ return icount_enabled() == 1; /* Precise instruction counting */
}
static uint64_t instructions_get_count(CPUARMState *env)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 26ae347b4a..e51ed7b9ca 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -299,7 +299,7 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (use_icount) {
+ if (icount_enabled()) {
*val = cpu_get_icount();
} else {
*val = cpu_get_host_ticks();
@@ -314,7 +314,7 @@ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (use_icount) {
+ if (icount_enabled()) {
*val = cpu_get_icount() >> 32;
} else {
*val = cpu_get_host_ticks() >> 32;